From 7896dee349bf747f5c03a9f5206a548b7482e72c Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Tue, 13 Jun 2017 17:01:16 -0700 Subject: [PATCH] anv/cnl: Don't write to Cache Mode Register 1 on gen10+ For PartialResolveDisableInVC field recommendation is to always set this to 0 and that's the default value of the bit. So, we have nothing left to write to CACHE_MODE_1. Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke --- src/intel/vulkan/genX_state.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 7a16ec06f71..3e6583289b6 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -52,13 +52,11 @@ genX(init_device_state)(struct anv_device *device) ps.PipelineSelection = _3D; } -#if GEN_GEN >= 9 +#if GEN_GEN == 9 uint32_t cache_mode_1; anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1), -#if GEN_GEN == 9 .FloatBlendOptimizationEnable = true, .FloatBlendOptimizationEnableMask = true, -#endif .PartialResolveDisableInVC = true, .PartialResolveDisableInVCMask = true); -- 2.30.2