From 7899a06ed64c55e8d804ef2970ad983e3d112013 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 19:59:24 -0700
Subject: [PATCH] Another typo

---
 techlibs/xilinx/abc_ff.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 91cfbc4c4..6f9011ef1 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -94,7 +94,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
+  \$__ABC_FDPE #(
     .INIT(|0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
-- 
2.30.2