From 78a701dc28427a07839f94bb34dafa8298dccaf7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Oct 2018 23:31:58 +0100
Subject: [PATCH] fmv/mvlq/fsq

---
 riscv/insns/fcvt_s_wu.h | 2 +-
 riscv/insns/fld.h       | 2 +-
 riscv/insns/flq.h       | 2 +-
 riscv/insns/flw.h       | 2 +-
 riscv/insns/fmv_x_w.h   | 2 +-
 riscv/insns/fsd.h       | 2 +-
 riscv/insns/fsq.h       | 2 +-
 riscv/insns/fsw.h       | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index c1394c3..b3cade4 100644
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f32((uint32_t)RS1));
+WRITE_FRD(ui32_to_f32(sv_reg_uint32(RS1)));
 set_fp_exceptions;
diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 4dea1d4..c63fdd8 100644
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64(MMU.load_uint64(RS1 + insn.i_imm())));
+WRITE_FRD(f64(MMU.load_uint64(rv_add(RS1, insn.i_imm()))));
diff --git a/riscv/insns/flq.h b/riscv/insns/flq.h
index 81d225c..0e371ef 100644
--- a/riscv/insns/flq.h
+++ b/riscv/insns/flq.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-WRITE_FRD(MMU.load_float128(RS1 + insn.i_imm()));
+WRITE_FRD(MMU.load_float128(rv_add(RS1, insn.i_imm())));
diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 6129754..301b9b2 100644
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32(MMU.load_uint32(RS1 + insn.i_imm())));
+WRITE_FRD(f32(MMU.load_uint32(rv_add(RS1, insn.i_imm()))));
diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index 6754f86..ca23310 100644
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(FRS1.v[0]));
+WRITE_RD(sext32(sv_reg_t(FRS1.v[0])));
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 38c702b..f1a76ab 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v[0]);
+MMU.store_uint64(rv_add(RS1, insn.s_imm()), FRS2.v[0]);
diff --git a/riscv/insns/fsq.h b/riscv/insns/fsq.h
index 610960e..b3e9c08 100644
--- a/riscv/insns/fsq.h
+++ b/riscv/insns/fsq.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-MMU.store_float128(RS1 + insn.s_imm(), FRS2);
+MMU.store_float128(rv_add(RS1, insn.s_imm()), FRS2);
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 8af5184..226e30e 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]);
+MMU.store_uint32(rv_add(RS1, insn.s_imm()), FRS2.v[0]);
-- 
2.30.2