From 78addeae5315886ffcb86c8610c71a6f7fc13abd Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 30 Mar 2023 11:09:01 +0100 Subject: [PATCH] aarch64: Add sme-i16i64 and sme-f64f64 aliases Most extension flags are named after the associated architectural FEAT_* flags, but sme-i64 and sme-f64 were exceptions. This patch adds sme-i16i64 and sme-f64f64 aliases, but keeps the old names too for compatibility. --- gas/config/tc-aarch64.c | 8 +- gas/doc/c-aarch64.texi | 8 +- gas/testsuite/gas/aarch64/sme-f64f64.d | 32 +++++++ gas/testsuite/gas/aarch64/sme-i16i64.d | 118 +++++++++++++++++++++++++ include/opcode/aarch64.h | 4 +- opcodes/aarch64-tbl.h | 44 ++++----- 6 files changed, 184 insertions(+), 30 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme-f64f64.d create mode 100644 gas/testsuite/gas/aarch64/sme-i16i64.d diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c1736c2c684..eb28ea3dce2 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10156,9 +10156,13 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME, 0), AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_BFLOAT16, 0)}, - {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64, 0), + {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64, 0), AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, - {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64, 0), + {"sme-f64f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64F64, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, + {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, + {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0), AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0), AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)}, diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 8aee80b7ebb..3921c0d368e 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -231,10 +231,10 @@ automatically cause those extensions to be disabled. @code{fp} and @code{simd}. @item @code{sme} @tab Armv9-A @tab No @tab Enable SME Extension. -@item @code{sme-f64} @tab Armv9-A @tab No - @tab Enable SME F64 Extension. -@item @code{sme-i64} @tab Armv9-A @tab No - @tab Enable SME I64 Extension. +@item @code{sme-f64f64} @tab Armv9-A @tab No + @tab Enable SME F64F64 Extension. +@item @code{sme-i16i64} @tab Armv9-A @tab No + @tab Enable SME I16I64 Extension. @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later @tab Enable Speculative Store Bypassing Safe state read and write. @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later diff --git a/gas/testsuite/gas/aarch64/sme-f64f64.d b/gas/testsuite/gas/aarch64/sme-f64f64.d new file mode 100644 index 00000000000..b45241598f4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-f64f64.d @@ -0,0 +1,32 @@ +#name: SME F64 extension +#as: -march=armv8-a+sme-f64f64 +#source: sme-f64.s +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: 80c82020 fmopa za0.d, p0/m, p1/m, z1.d, z8.d + 4: 80c76841 fmopa za1.d, p2/m, p3/m, z2.d, z7.d + 8: 80c6b062 fmopa za2.d, p4/m, p5/m, z3.d, z6.d + c: 80c5f883 fmopa za3.d, p6/m, p7/m, z4.d, z5.d + 10: 80c404a4 fmopa za4.d, p1/m, p0/m, z5.d, z4.d + 14: 80c34cc5 fmopa za5.d, p3/m, p2/m, z6.d, z3.d + 18: 80c294e6 fmopa za6.d, p5/m, p4/m, z7.d, z2.d + 1c: 80c1dd07 fmopa za7.d, p7/m, p6/m, z8.d, z1.d + 20: 80c41ca4 fmopa za4.d, p7/m, p0/m, z5.d, z4.d + 24: 80c338c5 fmopa za5.d, p6/m, p1/m, z6.d, z3.d + 28: 80c254e6 fmopa za6.d, p5/m, p2/m, z7.d, z2.d + 2c: 80c17107 fmopa za7.d, p4/m, p3/m, z8.d, z1.d + 30: 80c82030 fmops za0.d, p0/m, p1/m, z1.d, z8.d + 34: 80c76851 fmops za1.d, p2/m, p3/m, z2.d, z7.d + 38: 80c6b072 fmops za2.d, p4/m, p5/m, z3.d, z6.d + 3c: 80c5f893 fmops za3.d, p6/m, p7/m, z4.d, z5.d + 40: 80c404b4 fmops za4.d, p1/m, p0/m, z5.d, z4.d + 44: 80c34cd5 fmops za5.d, p3/m, p2/m, z6.d, z3.d + 48: 80c294f6 fmops za6.d, p5/m, p4/m, z7.d, z2.d + 4c: 80c1dd17 fmops za7.d, p7/m, p6/m, z8.d, z1.d + 50: 81a1f803 fmopa za3.s, p6/m, p7/m, z0.h, z1.h + 54: 8081f813 fmops za3.s, p6/m, p7/m, z0.s, z1.s diff --git a/gas/testsuite/gas/aarch64/sme-i16i64.d b/gas/testsuite/gas/aarch64/sme-i16i64.d new file mode 100644 index 00000000000..1fa1fb6a537 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-i16i64.d @@ -0,0 +1,118 @@ +#name: SME I64 extension +#as: -march=armv8-a+sme-i16i64 +#source: sme-i64.s +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: c0d02020 addha za0.d, p0/m, p1/m, z1.d + 4: c0d06841 addha za1.d, p2/m, p3/m, z2.d + 8: c0d0b062 addha za2.d, p4/m, p5/m, z3.d + c: c0d0f883 addha za3.d, p6/m, p7/m, z4.d + 10: c0d004a4 addha za4.d, p1/m, p0/m, z5.d + 14: c0d04cc5 addha za5.d, p3/m, p2/m, z6.d + 18: c0d094e6 addha za6.d, p5/m, p4/m, z7.d + 1c: c0d0dd07 addha za7.d, p7/m, p6/m, z8.d + 20: c0d01ca4 addha za4.d, p7/m, p0/m, z5.d + 24: c0d038c5 addha za5.d, p6/m, p1/m, z6.d + 28: c0d054e6 addha za6.d, p5/m, p2/m, z7.d + 2c: c0d07107 addha za7.d, p4/m, p3/m, z8.d + 30: c0d12020 addva za0.d, p0/m, p1/m, z1.d + 34: c0d16841 addva za1.d, p2/m, p3/m, z2.d + 38: c0d1b062 addva za2.d, p4/m, p5/m, z3.d + 3c: c0d1f883 addva za3.d, p6/m, p7/m, z4.d + 40: c0d104a4 addva za4.d, p1/m, p0/m, z5.d + 44: c0d14cc5 addva za5.d, p3/m, p2/m, z6.d + 48: c0d194e6 addva za6.d, p5/m, p4/m, z7.d + 4c: c0d1dd07 addva za7.d, p7/m, p6/m, z8.d + 50: c0d11ca4 addva za4.d, p7/m, p0/m, z5.d + 54: c0d138c5 addva za5.d, p6/m, p1/m, z6.d + 58: c0d154e6 addva za6.d, p5/m, p2/m, z7.d + 5c: c0d17107 addva za7.d, p4/m, p3/m, z8.d + 60: a0c82020 smopa za0.d, p0/m, p1/m, z1.h, z8.h + 64: a0c76841 smopa za1.d, p2/m, p3/m, z2.h, z7.h + 68: a0c6b062 smopa za2.d, p4/m, p5/m, z3.h, z6.h + 6c: a0c5f883 smopa za3.d, p6/m, p7/m, z4.h, z5.h + 70: a0c404a4 smopa za4.d, p1/m, p0/m, z5.h, z4.h + 74: a0c34cc5 smopa za5.d, p3/m, p2/m, z6.h, z3.h + 78: a0c294e6 smopa za6.d, p5/m, p4/m, z7.h, z2.h + 7c: a0c1dd07 smopa za7.d, p7/m, p6/m, z8.h, z1.h + 80: a0c82030 smops za0.d, p0/m, p1/m, z1.h, z8.h + 84: a0c76851 smops za1.d, p2/m, p3/m, z2.h, z7.h + 88: a0c6b072 smops za2.d, p4/m, p5/m, z3.h, z6.h + 8c: a0c5f893 smops za3.d, p6/m, p7/m, z4.h, z5.h + 90: a0c404b4 smops za4.d, p1/m, p0/m, z5.h, z4.h + 94: a0c34cd5 smops za5.d, p3/m, p2/m, z6.h, z3.h + 98: a0c294f6 smops za6.d, p5/m, p4/m, z7.h, z2.h + 9c: a0c1dd17 smops za7.d, p7/m, p6/m, z8.h, z1.h + a0: a0c41cb4 smops za4.d, p7/m, p0/m, z5.h, z4.h + a4: a0c338d5 smops za5.d, p6/m, p1/m, z6.h, z3.h + a8: a0c254f6 smops za6.d, p5/m, p2/m, z7.h, z2.h + ac: a0c17117 smops za7.d, p4/m, p3/m, z8.h, z1.h + b0: a0e82020 sumopa za0.d, p0/m, p1/m, z1.h, z8.h + b4: a0e76841 sumopa za1.d, p2/m, p3/m, z2.h, z7.h + b8: a0e6b062 sumopa za2.d, p4/m, p5/m, z3.h, z6.h + bc: a0e5f883 sumopa za3.d, p6/m, p7/m, z4.h, z5.h + c0: a0e404a4 sumopa za4.d, p1/m, p0/m, z5.h, z4.h + c4: a0e34cc5 sumopa za5.d, p3/m, p2/m, z6.h, z3.h + c8: a0e294e6 sumopa za6.d, p5/m, p4/m, z7.h, z2.h + cc: a0e1dd07 sumopa za7.d, p7/m, p6/m, z8.h, z1.h + d0: a0e82030 sumops za0.d, p0/m, p1/m, z1.h, z8.h + d4: a0e76851 sumops za1.d, p2/m, p3/m, z2.h, z7.h + d8: a0e6b072 sumops za2.d, p4/m, p5/m, z3.h, z6.h + dc: a0e5f893 sumops za3.d, p6/m, p7/m, z4.h, z5.h + e0: a0e404b4 sumops za4.d, p1/m, p0/m, z5.h, z4.h + e4: a0e34cd5 sumops za5.d, p3/m, p2/m, z6.h, z3.h + e8: a0e294f6 sumops za6.d, p5/m, p4/m, z7.h, z2.h + ec: a0e1dd17 sumops za7.d, p7/m, p6/m, z8.h, z1.h + f0: a1e82020 umopa za0.d, p0/m, p1/m, z1.h, z8.h + f4: a1e76841 umopa za1.d, p2/m, p3/m, z2.h, z7.h + f8: a1e6b062 umopa za2.d, p4/m, p5/m, z3.h, z6.h + fc: a1e5f883 umopa za3.d, p6/m, p7/m, z4.h, z5.h + 100: a1e404a4 umopa za4.d, p1/m, p0/m, z5.h, z4.h + 104: a1e34cc5 umopa za5.d, p3/m, p2/m, z6.h, z3.h + 108: a1e294e6 umopa za6.d, p5/m, p4/m, z7.h, z2.h + 10c: a1e1dd07 umopa za7.d, p7/m, p6/m, z8.h, z1.h + 110: a1e82030 umops za0.d, p0/m, p1/m, z1.h, z8.h + 114: a1e76851 umops za1.d, p2/m, p3/m, z2.h, z7.h + 118: a1e6b072 umops za2.d, p4/m, p5/m, z3.h, z6.h + 11c: a1e5f893 umops za3.d, p6/m, p7/m, z4.h, z5.h + 120: a1e404b4 umops za4.d, p1/m, p0/m, z5.h, z4.h + 124: a1e34cd5 umops za5.d, p3/m, p2/m, z6.h, z3.h + 128: a1e294f6 umops za6.d, p5/m, p4/m, z7.h, z2.h + 12c: a1e1dd17 umops za7.d, p7/m, p6/m, z8.h, z1.h + 130: a1c82020 usmopa za0.d, p0/m, p1/m, z1.h, z8.h + 134: a1c76841 usmopa za1.d, p2/m, p3/m, z2.h, z7.h + 138: a1c6b062 usmopa za2.d, p4/m, p5/m, z3.h, z6.h + 13c: a1c5f883 usmopa za3.d, p6/m, p7/m, z4.h, z5.h + 140: a1c404a4 usmopa za4.d, p1/m, p0/m, z5.h, z4.h + 144: a1c34cc5 usmopa za5.d, p3/m, p2/m, z6.h, z3.h + 148: a1c294e6 usmopa za6.d, p5/m, p4/m, z7.h, z2.h + 14c: a1c1dd07 usmopa za7.d, p7/m, p6/m, z8.h, z1.h + 150: a1c82030 usmops za0.d, p0/m, p1/m, z1.h, z8.h + 154: a1c76851 usmops za1.d, p2/m, p3/m, z2.h, z7.h + 158: a1c6b072 usmops za2.d, p4/m, p5/m, z3.h, z6.h + 15c: a1c5f893 usmops za3.d, p6/m, p7/m, z4.h, z5.h + 160: a1c404b4 usmops za4.d, p1/m, p0/m, z5.h, z4.h + 164: a1c34cd5 usmops za5.d, p3/m, p2/m, z6.h, z3.h + 168: a1c294f6 usmops za6.d, p5/m, p4/m, z7.h, z2.h + 16c: a1c1dd17 usmops za7.d, p7/m, p6/m, z8.h, z1.h + 170: a1c41cb4 usmops za4.d, p7/m, p0/m, z5.h, z4.h + 174: a1c338d5 usmops za5.d, p6/m, p1/m, z6.h, z3.h + 178: a1c254f6 usmops za6.d, p5/m, p2/m, z7.h, z2.h + 17c: a1c17117 usmops za7.d, p4/m, p3/m, z8.h, z1.h + 180: c0d02020 addha za0.d, p0/m, p1/m, z1.d + 184: c0d17107 addva za7.d, p4/m, p3/m, z8.d + 188: 8181f883 bfmopa za3.s, p6/m, p7/m, z4.h, z1.h + 18c: 8181f893 bfmops za3.s, p6/m, p7/m, z4.h, z1.h + 190: a0c1dd07 smopa za7.d, p7/m, p6/m, z8.h, z1.h + 194: a0c17117 smops za7.d, p4/m, p3/m, z8.h, z1.h + 198: a0e1dd07 sumopa za7.d, p7/m, p6/m, z8.h, z1.h + 19c: a0e1dd17 sumops za7.d, p7/m, p6/m, z8.h, z1.h + 1a0: a1a1f883 umopa za3.s, p6/m, p7/m, z4.b, z1.b + 1a4: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b + 1a8: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b + 1ac: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 40b2fdbc893..d0a0b629d99 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -96,8 +96,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_F64MM (1ULL << 54) #define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */ #define AARCH64_FEATURE_V9 (1ULL << 56) /* Armv9.0-A processors. */ -#define AARCH64_FEATURE_SME_F64 (1ULL << 57) /* SME F64. */ -#define AARCH64_FEATURE_SME_I64 (1ULL << 58) /* SME I64. */ +#define AARCH64_FEATURE_SME_F64F64 (1ULL << 57) /* SME F64F64. */ +#define AARCH64_FEATURE_SME_I16I64 (1ULL << 58) /* SME I16I64. */ #define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */ #define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 511c439f96d..69703650471 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2475,12 +2475,12 @@ static const aarch64_feature_set aarch64_feature_sve2bitperm = AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0); static const aarch64_feature_set aarch64_feature_sme = AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME, 0); -static const aarch64_feature_set aarch64_feature_sme_f64 = +static const aarch64_feature_set aarch64_feature_sme_f64f64 = AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME - | AARCH64_FEATURE_SME_F64, 0); -static const aarch64_feature_set aarch64_feature_sme_i64 = + | AARCH64_FEATURE_SME_F64F64, 0); +static const aarch64_feature_set aarch64_feature_sme_i16i64 = AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME - | AARCH64_FEATURE_SME_I64, 0); + | AARCH64_FEATURE_SME_I16I64, 0); static const aarch64_feature_set aarch64_feature_v8_6 = AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0); static const aarch64_feature_set aarch64_feature_v8_7 = @@ -2547,8 +2547,8 @@ static const aarch64_feature_set aarch64_feature_cssc = #define SVE2_SM4 &aarch64_feature_sve2sm4 #define SVE2_BITPERM &aarch64_feature_sve2bitperm #define SME &aarch64_feature_sme -#define SME_F64 &aarch64_feature_sme_f64 -#define SME_I64 &aarch64_feature_sme_i64 +#define SME_F64F64 &aarch64_feature_sme_f64f64 +#define SME_I16I64 &aarch64_feature_sme_i16i64 #define ARMV8_6 &aarch64_feature_v8_6 #define ARMV8_6_SVE &aarch64_feature_v8_6 #define BFLOAT16_SVE &aarch64_feature_bfloat16_sve @@ -2651,11 +2651,11 @@ static const aarch64_feature_set aarch64_feature_cssc = #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ FLAGS, 0, TIED, NULL } -#define SME_F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, OP, SME_F64, OPS, QUALS, \ +#define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \ FLAGS, 0, TIED, NULL } -#define SME_I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, OP, SME_I64, OPS, QUALS, \ +#define SME_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME_I16I64, OPS, QUALS, \ FLAGS, 0, TIED, NULL } #define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ @@ -5207,36 +5207,36 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), /* SME instructions. */ SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), - SME_I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), + SME_I16I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), SME_INSN ("addspl", 0x04605800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), SME_INSN ("addsvl", 0x04205800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), - SME_I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), + SME_I16I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0), SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0), SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0), - SME_F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), + SME_F64F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0), SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0), - SME_F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), + SME_F64F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0), SME_INSN ("rdsvl", 0x04bf5800, 0xfffff800, sme_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0), SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), - SME_I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), -- 2.30.2