From 78bb49c10ccd569f3039e81689731bbdf6130fa7 Mon Sep 17 00:00:00 2001
From: whitequark <cz@m-labs.hk>
Date: Tue, 4 Jun 2019 08:18:50 +0000
Subject: [PATCH] Clean up imports.

This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
---
 nmigen/__init__.py                  | 12 ++----------
 nmigen/formal.py                    |  1 +
 nmigen/hdl/__init__.py              |  7 +++++++
 nmigen/lib/__init__.py              |  1 +
 nmigen/test/test_lib_cdc.py         |  4 +---
 nmigen/test/test_lib_coding.py      |  5 ++---
 nmigen/test/test_lib_fifo.py        |  8 ++------
 nmigen/test/test_lib_io.py          |  3 ++-
 nmigen/vendor/fpga/lattice_ice40.py |  4 +---
 9 files changed, 19 insertions(+), 26 deletions(-)

diff --git a/nmigen/__init__.py b/nmigen/__init__.py
index 17ddfea..d2aa2ba 100644
--- a/nmigen/__init__.py
+++ b/nmigen/__init__.py
@@ -2,13 +2,5 @@ from ._version import get_versions
 __version__ = get_versions()['version']
 del get_versions
 
-from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
-from .hdl.dsl import Module
-from .hdl.cd import ClockDomain
-from .hdl.ir import Elaboratable, Fragment, Instance
-from .hdl.mem import Memory
-from .hdl.rec import Record
-from .hdl.xfrm import ResetInserter, CEInserter
-
-from .lib.cdc import MultiReg
-# from .lib.io import
+from .hdl import *
+from .lib import *
diff --git a/nmigen/formal.py b/nmigen/formal.py
index 3d97b33..2836cca 100644
--- a/nmigen/formal.py
+++ b/nmigen/formal.py
@@ -1 +1,2 @@
 from .hdl.ast import AnyConst, AnySeq, Assert, Assume
+from .hdl.ast import Past, Stable, Rose, Fell
diff --git a/nmigen/hdl/__init__.py b/nmigen/hdl/__init__.py
index e69de29..388d1ce 100644
--- a/nmigen/hdl/__init__.py
+++ b/nmigen/hdl/__init__.py
@@ -0,0 +1,7 @@
+from .ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
+from .dsl import Module
+from .cd import ClockDomain
+from .ir import Elaboratable, Fragment, Instance
+from .mem import Memory
+from .rec import Record
+from .xfrm import DomainRenamer, ResetInserter, CEInserter
diff --git a/nmigen/lib/__init__.py b/nmigen/lib/__init__.py
index e69de29..cc3587b 100644
--- a/nmigen/lib/__init__.py
+++ b/nmigen/lib/__init__.py
@@ -0,0 +1 @@
+from .cdc import MultiReg
diff --git a/nmigen/test/test_lib_cdc.py b/nmigen/test/test_lib_cdc.py
index 4a6c1cf..9aea5d4 100644
--- a/nmigen/test/test_lib_cdc.py
+++ b/nmigen/test/test_lib_cdc.py
@@ -1,7 +1,5 @@
 from .tools import *
-from ..hdl.ast import *
-from ..hdl.cd import *
-from ..hdl.dsl import *
+from ..hdl import *
 from ..back.pysim import *
 from ..lib.cdc import *
 
diff --git a/nmigen/test/test_lib_coding.py b/nmigen/test/test_lib_coding.py
index 8c6b624..4cdd83f 100644
--- a/nmigen/test/test_lib_coding.py
+++ b/nmigen/test/test_lib_coding.py
@@ -1,7 +1,6 @@
 from .tools import *
-from ..hdl.ast import *
-from ..hdl.dsl import *
-from ..hdl.ir import *
+from ..hdl import *
+from ..formal import *
 from ..back.pysim import *
 from ..lib.coding import *
 
diff --git a/nmigen/test/test_lib_fifo.py b/nmigen/test/test_lib_fifo.py
index 3497186..735e00e 100644
--- a/nmigen/test/test_lib_fifo.py
+++ b/nmigen/test/test_lib_fifo.py
@@ -1,10 +1,6 @@
 from .tools import *
-from ..hdl.ast import *
-from ..hdl.dsl import *
-from ..hdl.mem import *
-from ..hdl.ir import *
-from ..hdl.xfrm import *
-from ..hdl.cd import *
+from ..hdl import *
+from ..formal import *
 from ..back.pysim import *
 from ..lib.fifo import *
 
diff --git a/nmigen/test/test_lib_io.py b/nmigen/test/test_lib_io.py
index 38f66cb..7ae44a3 100644
--- a/nmigen/test/test_lib_io.py
+++ b/nmigen/test/test_lib_io.py
@@ -1,6 +1,7 @@
 from .tools import *
-from ..hdl.ast import *
+from ..hdl import *
 from ..hdl.rec import *
+from ..back.pysim import *
 from ..lib.io import *
 
 
diff --git a/nmigen/vendor/fpga/lattice_ice40.py b/nmigen/vendor/fpga/lattice_ice40.py
index 43f5cb3..8dc2d2b 100644
--- a/nmigen/vendor/fpga/lattice_ice40.py
+++ b/nmigen/vendor/fpga/lattice_ice40.py
@@ -3,9 +3,7 @@ import os
 import subprocess
 import tempfile
 
-from ...hdl.ast import *
-from ...hdl.dsl import *
-from ...hdl.ir import *
+from ...hdl import *
 from ...build import *
 
 
-- 
2.30.2