From 78d900a0cab048804624709e337bd2c3a05d1efd Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 7 Apr 2022 00:11:22 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index ee1344924..3ee7c38ed 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -721,14 +721,17 @@ for i in 0 to VL-1: The reason why should be clear from this being a Vector loop: unconditional destruction of LR when LK=1 makes `bclrl` -ineffective. However if the change to LR only occurs if +ineffective, because the intention going into the loop is +that the branch should be to the copy of LR set at the *start* +of the loop, not half way through it. +However if the change to LR only occurs if the branch is taken then it becomes a useful instruction. The following pseudocode should **not** be implemented because it violates the fundamental principle of SVP64 which is that SVP64 looping is a thin wrapper around Scalar Instructions. The pseducode below is more an actual Vector ISA Branch and -as such is not aporopriate: +as such is not at all appropriate: ``` for i in 0 to VL-1: -- 2.30.2