From 78daf7118281872b5feace9cf0333474c9cfd720 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Apr 2020 18:22:56 +0100 Subject: [PATCH] add rtlil conversion and fix yield from in Cordic Data --- src/ieee754/cordic/pipe_data.py | 8 ++++---- src/ieee754/cordic/test/test_pipe.py | 8 ++++++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/ieee754/cordic/pipe_data.py b/src/ieee754/cordic/pipe_data.py index bcdeae9d..493331b0 100644 --- a/src/ieee754/cordic/pipe_data.py +++ b/src/ieee754/cordic/pipe_data.py @@ -10,7 +10,7 @@ class CordicInitialData: self.z0 = Signal(range(-ZMAX, ZMAX), name="z") # denormed result def __iter__(self): - yield from self.z + yield self.z0 def eq(self, i): return [self.z0.eq(i.z0)] @@ -27,9 +27,9 @@ class CordicData: self.z = Signal(range(-ZMAX, ZMAX), name="z") # denormed result def __iter__(self): - yield from self.x - yield from self.y - yield from self.z + yield self.x + yield self.y + yield self.z def eq(self, i): ret = [self.z.eq(i.z), self.x.eq(i.x), self.y.eq(i.y)] diff --git a/src/ieee754/cordic/test/test_pipe.py b/src/ieee754/cordic/test/test_pipe.py index 880351ad..b7eaf8ad 100644 --- a/src/ieee754/cordic/test/test_pipe.py +++ b/src/ieee754/cordic/test/test_pipe.py @@ -1,6 +1,7 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Passive from nmigen.test.utils import FHDLTestCase +from nmigen.cli import rtlil from ieee754.cordic.sin_cos_pipeline import CordicBasePipe from ieee754.cordic.pipe_data import CordicPipeSpec @@ -16,6 +17,13 @@ class SinCosTestCase(FHDLTestCase): pspec = CordicPipeSpec(fracbits=fracbits, rounds_per_stage=4) m.submodules.dut = dut = CordicBasePipe(pspec) + for port in dut.ports(): + print ("port", port) + + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_cordic_pipe_sin_cos.il", "w") as f: + f.write(vl) + z = Signal(dut.p.data_i.z0.shape()) z_valid = Signal() ready = Signal() -- 2.30.2