From 78ef1e3d9fbe214ead3c117ec54a5c10da91a0df Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 26 Jan 2005 15:18:14 -0800 Subject: [PATCH] re PR middle-end/18008 (Duplicate mask on bitfield insertion) PR middle-end/18008 * c-decl.c (finish_struct): Set DECL_MODE after resetting a field's type. * expmed.c (store_fixed_bit_field): Create a paradoxical subreg if we don't need the bits above those present in the current mode. * expr.c (store_field): Strip conversions to odd-bit-sized types if the destination field width matches. From-SVN: r94290 --- gcc/ChangeLog | 11 +++++++++++ gcc/c-decl.c | 7 +++++-- gcc/expmed.c | 2 +- gcc/expr.c | 16 +++++++++++++++- 4 files changed, 32 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 316c0505340..7b5f4dc2ca4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2005-01-26 Richard Henderson + + PR middle-end/18008 + * c-decl.c (finish_struct): Set DECL_MODE after resetting a + field's type. + * expmed.c (store_fixed_bit_field): Create a paradoxical subreg + if we don't need the bits above those present in the current mode. + * expr.c (store_field): Strip conversions to odd-bit-sized types + if the destination field width matches. + 2005-01-26 Richard Sandiford * config/mips/iris6.h (ENDFILE_SPEC): Don't link in irix-csr.o if @@ -33,6 +43,7 @@ * configure.ac: Check for a TLS capable gas. * configure: Regenerate. + 2005-01-26 Richard Henderson PR middle-end/18008 diff --git a/gcc/c-decl.c b/gcc/c-decl.c index 6673927eab6..61521e861c7 100644 --- a/gcc/c-decl.c +++ b/gcc/c-decl.c @@ -5301,8 +5301,11 @@ finish_struct (tree t, tree fieldlist, tree attributes) = tree_low_cst (DECL_INITIAL (*fieldlistp), 1); tree type = TREE_TYPE (*fieldlistp); if (width != TYPE_PRECISION (type)) - TREE_TYPE (*fieldlistp) - = build_nonstandard_integer_type (width, TYPE_UNSIGNED (type)); + { + TREE_TYPE (*fieldlistp) + = build_nonstandard_integer_type (width, TYPE_UNSIGNED (type)); + DECL_MODE (*fieldlistp) = TYPE_MODE (TREE_TYPE (*fieldlistp)); + } DECL_INITIAL (*fieldlistp) = 0; } else diff --git a/gcc/expmed.c b/gcc/expmed.c index 1091c454064..084a987fdc0 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -878,7 +878,7 @@ store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset, if (GET_MODE (value) != mode) { if ((REG_P (value) || GET_CODE (value) == SUBREG) - && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value))) + && GET_MODE_SIZE (GET_MODE (value)) <= bitsize) value = gen_lowpart (mode, value); else value = convert_to_mode (mode, value, 1); diff --git a/gcc/expr.c b/gcc/expr.c index ed693a3166f..1f82b1d9834 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -5215,7 +5215,21 @@ store_field (rtx target, HOST_WIDE_INT bitsize, HOST_WIDE_INT bitpos, && TREE_CODE (TYPE_SIZE (TREE_TYPE (exp))) == INTEGER_CST && compare_tree_int (TYPE_SIZE (TREE_TYPE (exp)), bitsize) != 0)) { - rtx temp = expand_expr (exp, NULL_RTX, VOIDmode, 0); + rtx temp; + + /* If EXP is a NOP_EXPR of precision less than its mode, then that + implies a mask operation. If the precision is the same size as + the field we're storing into, that mask is redundant. This is + particularly common with bit field assignments generated by the + C front end. */ + if (TREE_CODE (exp) == NOP_EXPR + && INTEGRAL_TYPE_P (TREE_TYPE (exp)) + && (TYPE_PRECISION (TREE_TYPE (exp)) + < GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (exp)))) + && bitsize == TYPE_PRECISION (TREE_TYPE (exp))) + exp = TREE_OPERAND (exp, 0); + + temp = expand_expr (exp, NULL_RTX, VOIDmode, 0); /* If BITSIZE is narrower than the size of the type of EXP we will be narrowing TEMP. Normally, what's wanted are the -- 2.30.2