From 790c8ad018b2048008d216666a33522682df0afb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jun 2020 16:03:12 +0100 Subject: [PATCH] add msr to ISA in test_core.py --- src/soc/simple/test/test_core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 17742940..cd8ca928 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -77,7 +77,8 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem) + sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem, + test.msr) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) -- 2.30.2