From 790eb05a920bed17df985327971cf75428d8852d Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 15 Dec 2018 14:23:42 +0000 Subject: [PATCH] =?utf8?q?Rename=20fhdl=E2=86=92hdl,=20genlib=E2=86=92lib.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- doc/COMPAT_SUMMARY.md | 32 +++++++++++++++--------------- nmigen/__init__.py | 12 +++++------ nmigen/back/pysim.py | 4 ++-- nmigen/back/rtlil.py | 2 +- nmigen/compat/fhdl/bitcontainer.py | 2 +- nmigen/compat/fhdl/module.py | 2 +- nmigen/compat/fhdl/specials.py | 2 +- nmigen/compat/fhdl/structure.py | 6 +++--- nmigen/compat/genlib/cdc.py | 2 +- nmigen/compat/genlib/fsm.py | 4 ++-- nmigen/{fhdl => hdl}/__init__.py | 0 nmigen/{fhdl => hdl}/ast.py | 0 nmigen/{fhdl => hdl}/cd.py | 0 nmigen/{fhdl => hdl}/dsl.py | 0 nmigen/{fhdl => hdl}/ir.py | 0 nmigen/{fhdl => hdl}/xfrm.py | 0 nmigen/{genlib => lib}/__init__.py | 0 nmigen/{genlib => lib}/cdc.py | 2 +- nmigen/{genlib => lib}/io.py | 2 +- nmigen/test/test_fhdl_ast.py | 2 +- nmigen/test/test_fhdl_cd.py | 2 +- nmigen/test/test_fhdl_dsl.py | 4 ++-- nmigen/test/test_fhdl_ir.py | 6 +++--- nmigen/test/test_fhdl_xfrm.py | 8 ++++---- nmigen/test/test_sim.py | 4 ++-- nmigen/test/tools.py | 2 +- 26 files changed, 50 insertions(+), 50 deletions(-) rename nmigen/{fhdl => hdl}/__init__.py (100%) rename nmigen/{fhdl => hdl}/ast.py (100%) rename nmigen/{fhdl => hdl}/cd.py (100%) rename nmigen/{fhdl => hdl}/dsl.py (100%) rename nmigen/{fhdl => hdl}/ir.py (100%) rename nmigen/{fhdl => hdl}/xfrm.py (100%) rename nmigen/{genlib => lib}/__init__.py (100%) rename nmigen/{genlib => lib}/cdc.py (97%) rename nmigen/{genlib => lib}/io.py (96%) diff --git a/doc/COMPAT_SUMMARY.md b/doc/COMPAT_SUMMARY.md index 658b762..774a339 100644 --- a/doc/COMPAT_SUMMARY.md +++ b/doc/COMPAT_SUMMARY.md @@ -27,13 +27,13 @@ Status legend: Compatibility summary --------------------- - - (−) `fhdl` + - (−) `fhdl` → `.hdl` - (+) `bitcontainer` ⇒ `.tools` - (+) `log2_int` id - (+) `bits_for` id - (+) `value_bits_sign` → `Value.shape` - (−) `conv_output` ? - - (+) `decorators` ⇒ `.fhdl.xfrm` + - (+) `decorators` ⇒ `.hdl.xfrm`
Note: `transform_*` methods not considered part of public API. - (⊙) `ModuleTransformer` **brk** - (⊙) `ControlInserter` **brk** @@ -41,9 +41,9 @@ Compatibility summary - (+) `ResetInserter` id, `clock_domains=`→`controls=` - (+) `ClockDomainsRenamer` → `DomainRenamer`, `cd_remapping=`→`domain_map=` - (⊙) `edif` **brk** - - (+) `module` **obs** → `.fhdl.dsl` + - (+) `module` **obs** → `.hdl.dsl` - (+) `FinalizeError` **obs** - - (+) `Module` **obs** → `.fhdl.dsl.Module` + - (+) `Module` **obs** → `.hdl.dsl.Module` - (⊙) `namer` **brk** - (−) `simplify` ? - (−) `FullMemoryWE` ? @@ -52,12 +52,12 @@ Compatibility summary - (−) `specials` **obs** - (−) `Special` ? - (−) `Tristate` ? - - (+) `TSTriple` → `.genlib.io.TSTriple`, `bits_sign=`→`shape=` + - (+) `TSTriple` → `.lib.io.TSTriple`, `bits_sign=`→`shape=` - (−) `Instance` ? - (−) `READ_FIRST`/`WRITE_FIRST`/`NO_CHANGE` ? - (−) `_MemoryPort` ? - (−) `Memory` ? - - (−) `structure` → `.fhdl.ast` + - (−) `structure` → `.hdl.ast` - (+) `DUID` id - (+) `_Value` → `Value`
Note: values no longer valid as keys in `dict` and `set`; use `ValueDict` and `ValueSet` instead. @@ -75,14 +75,14 @@ Compatibility summary - (+) `_Statement` → `Statement` - (+) `_Assign` → `Assign`, `l=`→`lhs=`, `r=`→`rhs=` - (-) `_check_statement` **obs** → `Statement.wrap` - - (+) `If` **obs** → `.fhdl.dsl.Module.If` - - (+) `Case` **obs** → `.fhdl.dsl.Module.Switch` + - (+) `If` **obs** → `.hdl.dsl.Module.If` + - (+) `Case` **obs** → `.hdl.dsl.Module.Switch` - (−) `_ArrayProxy` ? - (−) `Array` ? - - (+) `ClockDomain` → `.fhdl.cd.ClockDomain` + - (+) `ClockDomain` → `.hdl.cd.ClockDomain` - (−) `_ClockDomainList` ? - (−) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` ? - - (⊙) `_Fragment` **brk** → `.fhdl.ir.Fragment` + - (⊙) `_Fragment` **brk** → `.hdl.ir.Fragment` - (−) `tools` **brk** - (−) `list_signals` ? - (−) `list_targets` ? @@ -94,12 +94,12 @@ Compatibility summary - (−) `is_variable` ? - (⊙) `generate_reset` **brk** - (⊙) `insert_reset` **brk** - - (⊙) `insert_resets` **brk** → `.fhdl.xfrm.ResetInserter` + - (⊙) `insert_resets` **brk** → `.hdl.xfrm.ResetInserter` - (⊙) `lower_basics` **brk** - (⊙) `lower_complex_slices` **brk** - (⊙) `lower_complex_parts` **brk** - (⊙) `rename_clock_domain_expr` **brk** - - (⊙) `rename_clock_domain` **brk** → `.fhdl.xfrm.DomainRenamer` + - (⊙) `rename_clock_domain` **brk** → `.hdl.xfrm.DomainRenamer` - (⊙) `call_special_classmethod` **brk** - (⊙) `lower_specials` **brk** - (−) `tracer` **brk** @@ -111,10 +111,10 @@ Compatibility summary - (−) `verilog` - (−) `DummyAttrTranslate` ? - (−) `convert` **obs** → `.back.verilog.convert` - - (⊙) `visit` **brk** → `.fhdl.xfrm` + - (⊙) `visit` **brk** → `.hdl.xfrm` - (⊙) `NodeVisitor` **brk** - - (⊙) `NodeTransformer` **brk** → `.fhdl.xfrm.ValueTransformer`/`.fhdl.xfrm.StatementTransformer` - - (−) `genlib` + - (⊙) `NodeTransformer` **brk** → `.hdl.xfrm.ValueTransformer`/`.hdl.xfrm.StatementTransformer` + - (−) `genlib` → `.lib` - (−) `cdc` ? - (−) `MultiRegImpl` ? - (+) `MultiReg` id @@ -177,7 +177,7 @@ Compatibility summary - (⊙) `vcd` **brk** → `vcd` - (⊙) `Simulator` **brk** - (+) `run_simulation` **obs** → `.back.pysim.Simulator` - - (−) `passive` **obs** → `.fhdl.ast.Passive` + - (−) `passive` **obs** → `.hdl.ast.Passive` - (−) `build` ? - (+) `util` **obs** - (+) `misc` ⇒ `.tools` diff --git a/nmigen/__init__.py b/nmigen/__init__.py index 36b1791..739d4df 100644 --- a/nmigen/__init__.py +++ b/nmigen/__init__.py @@ -1,7 +1,7 @@ -from .fhdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal -from .fhdl.dsl import Module -from .fhdl.cd import ClockDomain -from .fhdl.ir import Fragment -from .fhdl.xfrm import ResetInserter, CEInserter +from .hdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal +from .hdl.dsl import Module +from .hdl.cd import ClockDomain +from .hdl.ir import Fragment +from .hdl.xfrm import ResetInserter, CEInserter -from .genlib.cdc import MultiReg +from .lib.cdc import MultiReg diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 69ddf12..634dd20 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -5,8 +5,8 @@ from vcd import VCDWriter from vcd.gtkw import GTKWSave from ..tools import flatten -from ..fhdl.ast import * -from ..fhdl.xfrm import ValueTransformer, StatementTransformer +from ..hdl.ast import * +from ..hdl.xfrm import ValueTransformer, StatementTransformer __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"] diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index fc7420f..356e0f5 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -3,7 +3,7 @@ import textwrap from collections import defaultdict, OrderedDict from contextlib import contextmanager -from ..fhdl import ast, ir, xfrm +from ..hdl import ast, ir, xfrm class _Namer: diff --git a/nmigen/compat/fhdl/bitcontainer.py b/nmigen/compat/fhdl/bitcontainer.py index cbd6e88..5764f83 100644 --- a/nmigen/compat/fhdl/bitcontainer.py +++ b/nmigen/compat/fhdl/bitcontainer.py @@ -1,5 +1,5 @@ from ... import tools -from ...fhdl import ast +from ...hdl import ast from ...tools import deprecated diff --git a/nmigen/compat/fhdl/module.py b/nmigen/compat/fhdl/module.py index 53ff6b4..a9730ae 100644 --- a/nmigen/compat/fhdl/module.py +++ b/nmigen/compat/fhdl/module.py @@ -1,7 +1,7 @@ from collections.abc import Iterable from ...tools import flatten, deprecated -from ...fhdl import dsl +from ...hdl import dsl __all__ = ["Module", "FinalizeError"] diff --git a/nmigen/compat/fhdl/specials.py b/nmigen/compat/fhdl/specials.py index c60ee21..a043af1 100644 --- a/nmigen/compat/fhdl/specials.py +++ b/nmigen/compat/fhdl/specials.py @@ -1,4 +1,4 @@ -from ...genlib.io import TSTriple as NativeTSTriple +from ...lib.io import TSTriple as NativeTSTriple __all__ = ["TSTriple"] diff --git a/nmigen/compat/fhdl/structure.py b/nmigen/compat/fhdl/structure.py index 5a4d9fa..95c68c2 100644 --- a/nmigen/compat/fhdl/structure.py +++ b/nmigen/compat/fhdl/structure.py @@ -1,9 +1,9 @@ from collections import OrderedDict from ...tools import deprecated -from ...fhdl import ast -from ...fhdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal -from ...fhdl.cd import ClockDomain +from ...hdl import ast +from ...hdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal +from ...hdl.cd import ClockDomain __all__ = ["DUID", "wrap", "Mux", "Cat", "Replicate", "Constant", "C", "Signal", "ClockSignal", diff --git a/nmigen/compat/genlib/cdc.py b/nmigen/compat/genlib/cdc.py index e3c675c..2405df2 100644 --- a/nmigen/compat/genlib/cdc.py +++ b/nmigen/compat/genlib/cdc.py @@ -1,4 +1,4 @@ -from ...genlib.cdc import MultiReg +from ...lib.cdc import MultiReg __all__ = ["MultiReg"] diff --git a/nmigen/compat/genlib/fsm.py b/nmigen/compat/genlib/fsm.py index b6d2c88..88786e8 100644 --- a/nmigen/compat/genlib/fsm.py +++ b/nmigen/compat/genlib/fsm.py @@ -1,8 +1,8 @@ import warnings from collections import OrderedDict -from ...fhdl.xfrm import ValueTransformer, StatementTransformer -from ...fhdl.ast import * +from ...hdl.xfrm import ValueTransformer, StatementTransformer +from ...hdl.ast import * from ..fhdl.module import CompatModule, CompatFinalizeError from ..fhdl.structure import If, Case diff --git a/nmigen/fhdl/__init__.py b/nmigen/hdl/__init__.py similarity index 100% rename from nmigen/fhdl/__init__.py rename to nmigen/hdl/__init__.py diff --git a/nmigen/fhdl/ast.py b/nmigen/hdl/ast.py similarity index 100% rename from nmigen/fhdl/ast.py rename to nmigen/hdl/ast.py diff --git a/nmigen/fhdl/cd.py b/nmigen/hdl/cd.py similarity index 100% rename from nmigen/fhdl/cd.py rename to nmigen/hdl/cd.py diff --git a/nmigen/fhdl/dsl.py b/nmigen/hdl/dsl.py similarity index 100% rename from nmigen/fhdl/dsl.py rename to nmigen/hdl/dsl.py diff --git a/nmigen/fhdl/ir.py b/nmigen/hdl/ir.py similarity index 100% rename from nmigen/fhdl/ir.py rename to nmigen/hdl/ir.py diff --git a/nmigen/fhdl/xfrm.py b/nmigen/hdl/xfrm.py similarity index 100% rename from nmigen/fhdl/xfrm.py rename to nmigen/hdl/xfrm.py diff --git a/nmigen/genlib/__init__.py b/nmigen/lib/__init__.py similarity index 100% rename from nmigen/genlib/__init__.py rename to nmigen/lib/__init__.py diff --git a/nmigen/genlib/cdc.py b/nmigen/lib/cdc.py similarity index 97% rename from nmigen/genlib/cdc.py rename to nmigen/lib/cdc.py index 396e45a..db5af35 100644 --- a/nmigen/genlib/cdc.py +++ b/nmigen/lib/cdc.py @@ -1,4 +1,4 @@ -from ..fhdl import * +from .. import * __all__ = ["MultiReg"] diff --git a/nmigen/genlib/io.py b/nmigen/lib/io.py similarity index 96% rename from nmigen/genlib/io.py rename to nmigen/lib/io.py index b308b10..684e58f 100644 --- a/nmigen/genlib/io.py +++ b/nmigen/lib/io.py @@ -1,4 +1,4 @@ -from ..fhdl import * +from .. import * __all__ = ["TSTriple"] diff --git a/nmigen/test/test_fhdl_ast.py b/nmigen/test/test_fhdl_ast.py index fd1d58f..0fde4c6 100644 --- a/nmigen/test/test_fhdl_ast.py +++ b/nmigen/test/test_fhdl_ast.py @@ -1,4 +1,4 @@ -from ..fhdl.ast import * +from ..hdl.ast import * from .tools import * diff --git a/nmigen/test/test_fhdl_cd.py b/nmigen/test/test_fhdl_cd.py index 7dc7fe4..8e7dcdf 100644 --- a/nmigen/test/test_fhdl_cd.py +++ b/nmigen/test/test_fhdl_cd.py @@ -1,4 +1,4 @@ -from ..fhdl.cd import * +from ..hdl.cd import * from .tools import * diff --git a/nmigen/test/test_fhdl_dsl.py b/nmigen/test/test_fhdl_dsl.py index f8b109e..f156880 100644 --- a/nmigen/test/test_fhdl_dsl.py +++ b/nmigen/test/test_fhdl_dsl.py @@ -1,5 +1,5 @@ -from ..fhdl.ast import * -from ..fhdl.dsl import * +from ..hdl.ast import * +from ..hdl.dsl import * from .tools import * diff --git a/nmigen/test/test_fhdl_ir.py b/nmigen/test/test_fhdl_ir.py index 0be0354..fcc1b2e 100644 --- a/nmigen/test/test_fhdl_ir.py +++ b/nmigen/test/test_fhdl_ir.py @@ -1,6 +1,6 @@ -from ..fhdl.ast import * -from ..fhdl.cd import * -from ..fhdl.ir import * +from ..hdl.ast import * +from ..hdl.cd import * +from ..hdl.ir import * from .tools import * diff --git a/nmigen/test/test_fhdl_xfrm.py b/nmigen/test/test_fhdl_xfrm.py index 861dcd0..428bad7 100644 --- a/nmigen/test/test_fhdl_xfrm.py +++ b/nmigen/test/test_fhdl_xfrm.py @@ -1,7 +1,7 @@ -from ..fhdl.ast import * -from ..fhdl.cd import * -from ..fhdl.ir import * -from ..fhdl.xfrm import * +from ..hdl.ast import * +from ..hdl.cd import * +from ..hdl.ir import * +from ..hdl.xfrm import * from .tools import * diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index 0e2b67d..f6446e9 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -1,6 +1,6 @@ from .tools import * -from ..fhdl.ast import * -from ..fhdl.ir import * +from ..hdl.ast import * +from ..hdl.ir import * from ..back.pysim import * diff --git a/nmigen/test/tools.py b/nmigen/test/tools.py index 297e7f9..097925b 100644 --- a/nmigen/test/tools.py +++ b/nmigen/test/tools.py @@ -3,7 +3,7 @@ import unittest import warnings from contextlib import contextmanager -from ..fhdl.ast import * +from ..hdl.ast import * __all__ = ["FHDLTestCase"] -- 2.30.2