From 7917ed98e03722499bdeac7f06a21a0401137dd4 Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 26 Sep 2023 11:34:14 +0100
Subject: [PATCH] Added english language description, spaces and brackets for
 lwzux instruction

---
 openpower/isa/fixedload.mdwn | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 502e29c2..06299114 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -399,6 +399,16 @@ Pseudo-code:
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    The word in storage addressed by EA is loaded into
+    RT[32:63]. RT[0:31] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
-- 
2.30.2