From 79596e54e13a20f4c3dd09abd4c45f93dce494a6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 11 Jun 2022 19:23:25 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 1ca042148..a9d4440f4 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -465,3 +465,20 @@ Mode. Instructions could modify CR Fields currently being used as Predicate Masks: detecting this is so horrendous for hardware resource utilisation and hardware complexity that, again, the decision is made to relax these constraints and for Software to take that into account. + +# Floating-Point "Single" becomes "Half" + +In several places in the Power ISA there are operations that are on +32-bit quantities in 64-bit registers. The best example is FP which +has 64-bit operations (`fadd`) and 32-bit operations (`fadds` or +FP Add "single"). Element-width overrides it would seem to +be unnecessary, under these circunstances. + +However, it is not possible for `fadds` to fit two elements into +64-bit: bear in mind that the FP32 bits are spread out across a 64 +bit register in FP64 format. The solution here was to consider the +"s" at the end of each instruction +to mean "half of the element's width". Thus, `sv.fadds/ew=32` +actually stores an FP16 spread out across the 32 bits of an +element, in FP32 format, where `sv.fadd/ew=32` stores a full +FP32 result into the full 32 bits. -- 2.30.2