From 79603491352555ab5508565845da01826cfd9430 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 13 Nov 2012 10:16:03 -0800 Subject: [PATCH] fix vector code simulation problem, turn on SR_U64 --- riscv/processor.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index e047126..cdcf536 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -24,7 +24,7 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, : sim(*_sim), mmu(*_mmu), id(_id) { reset(true); - set_pcr(PCR_SR, sr | SR_EF | SR_EV); + set_pcr(PCR_SR, SR_U64 | SR_EF | SR_EV); utidx = _utidx; // microthreads don't possess their own microthreads -- 2.30.2