From 7980118d74aae04479be3b9e9b59f95bf3bfbfe5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 16:39:30 -0700
Subject: [PATCH] Add ice40 box files

---
 techlibs/ice40/Makefile.inc   | 3 +++
 techlibs/ice40/cells.box      | 6 ++++++
 techlibs/ice40/cells_box.v    | 5 +++++
 techlibs/ice40/cells_sim.v    | 1 +
 techlibs/ice40/lut.lut        | 4 ++++
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 6 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ice40/cells.box
 create mode 100644 techlibs/ice40/cells_box.v
 create mode 100644 techlibs/ice40/lut.lut

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 723b59d6f..cd992bb24 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
new file mode 100644
index 000000000..e4cfb71e6
--- /dev/null
+++ b/techlibs/ice40/cells.box
@@ -0,0 +1,6 @@
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
new file mode 100644
index 000000000..cca88f9aa
--- /dev/null
+++ b/techlibs/ice40/cells_box.v
@@ -0,0 +1,5 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364b..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -881,6 +881,7 @@ module SB_WARMBOOT (
 );
 endmodule
 
+(* nomem2reg *)
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
new file mode 100644
index 000000000..48da89f46
--- /dev/null
+++ b/techlibs/ice40/lut.lut
@@ -0,0 +1,4 @@
+1	1	316
+2	1	316 379
+3	1	316 379 400
+4	1	316	379	400	449
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 6c77e5482..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -316,7 +316,14 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run(abc + " -dress -lut 4", "(skip if -noabc)");
+				if (abc == "abc9") {
+					run("read_verilog +/ice40/cells_box.v");
+					run("techmap -map +/techmap.v A:abc_box_id");
+					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run("blackbox A:abc_box_id");
+				}
+				else
+					run(abc + " -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
2.30.2