From 799c3309a7ca963a9924182f7343c9f6e47cbcdf Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:21:16 +0530 Subject: [PATCH] arch-power: Add sign-extend instructions This adds the following instructions. * Extend Sign Word (extsw[.]) Change-Id: Ia15fc69de665399f1c8d52ca00d2f7670d553b48 Signed-off-by: Sandipan Das --- src/arch/power/insts/integer.cc | 1 + src/arch/power/isa/decoder.isa | 1 + 2 files changed, 2 insertions(+) diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc index c937a6f8f..408ca8e08 100644 --- a/src/arch/power/insts/integer.cc +++ b/src/arch/power/insts/integer.cc @@ -301,6 +301,7 @@ IntLogicOp::generateDisassembly( printSecondSrc = false; } else if (!myMnemonic.compare("extsb") || !myMnemonic.compare("extsh") || + !myMnemonic.compare("extsw") || !myMnemonic.compare("cntlzw")) { printSecondSrc = false; } diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 0932ce4b3..681358234 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -497,6 +497,7 @@ decode PO default Unknown::unknown() { 412: orc({{ Ra = Rs | ~Rb; }}, true); 954: extsb({{ Ra = Rs_sb; }}, true); 922: extsh({{ Ra = Rs_sh; }}, true); + 986: extsw({{ Ra = Rs_sw; }}, true); 26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true); 508: cmpb({{ -- 2.30.2