From 79bbdf8e45f0961b800279afadb4bb74129d7034 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 24 Oct 2018 08:50:26 +0200 Subject: [PATCH] radv: implement image to image operations for R32G32B32 This should address the remaining failures in Batman Arkhman City. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107765 Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_bufimage.c | 320 ++++++++++++++++++++++++++++ src/amd/vulkan/radv_meta_copy.c | 8 +- src/amd/vulkan/radv_private.h | 5 + 3 files changed, 331 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 56f1620db53..6f074a70b4c 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -909,6 +909,216 @@ radv_device_finish_meta_itoi_state(struct radv_device *device) state->itoi.pipeline_3d, &state->alloc); } +static nir_shader * +build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev) +{ + nir_builder b; + const struct glsl_type *type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, + false, + false, + GLSL_TYPE_FLOAT); + nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL); + b.shader->info.name = ralloc_strdup(b.shader, "meta_itoi_r32g32b32_cs"); + b.shader->info.cs.local_size[0] = 16; + b.shader->info.cs.local_size[1] = 16; + b.shader->info.cs.local_size[2] = 1; + nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, + type, "input_img"); + input_img->data.descriptor_set = 0; + input_img->data.binding = 0; + + nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform, + type, "output_img"); + output_img->data.descriptor_set = 0; + output_img->data.binding = 1; + + nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0); + nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0); + nir_ssa_def *block_size = nir_imm_ivec4(&b, + b.shader->info.cs.local_size[0], + b.shader->info.cs.local_size[1], + b.shader->info.cs.local_size[2], 0); + + nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id); + + nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); + nir_intrinsic_set_base(src_offset, 0); + nir_intrinsic_set_range(src_offset, 24); + src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); + src_offset->num_components = 3; + nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 3, 32, "src_offset"); + nir_builder_instr_insert(&b, &src_offset->instr); + + nir_ssa_def *src_stride = nir_channel(&b, &src_offset->dest.ssa, 2); + + nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); + nir_intrinsic_set_base(dst_offset, 0); + nir_intrinsic_set_range(dst_offset, 24); + dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12)); + dst_offset->num_components = 3; + nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 3, 32, "dst_offset"); + nir_builder_instr_insert(&b, &dst_offset->instr); + + nir_ssa_def *dst_stride = nir_channel(&b, &dst_offset->dest.ssa, 2); + + nir_ssa_def *src_img_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa); + nir_ssa_def *dst_img_coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa); + + nir_ssa_def *src_global_pos = + nir_iadd(&b, + nir_imul(&b, nir_channel(&b, src_img_coord, 1), src_stride), + nir_imul(&b, nir_channel(&b, src_img_coord, 0), nir_imm_int(&b, 3))); + + nir_ssa_def *dst_global_pos = + nir_iadd(&b, + nir_imul(&b, nir_channel(&b, dst_img_coord, 1), dst_stride), + nir_imul(&b, nir_channel(&b, dst_img_coord, 0), nir_imm_int(&b, 3))); + + for (int chan = 0; chan < 3; chan++) { + /* src */ + nir_ssa_def *src_local_pos = + nir_iadd(&b, src_global_pos, nir_imm_int(&b, chan)); + + nir_ssa_def *src_coord = + nir_vec4(&b, src_local_pos, src_local_pos, + src_local_pos, src_local_pos); + + nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa; + + nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3); + tex->sampler_dim = GLSL_SAMPLER_DIM_BUF; + tex->op = nir_texop_txf; + tex->src[0].src_type = nir_tex_src_coord; + tex->src[0].src = nir_src_for_ssa(nir_channels(&b, src_coord, 1)); + tex->src[1].src_type = nir_tex_src_lod; + tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0)); + tex->src[2].src_type = nir_tex_src_texture_deref; + tex->src[2].src = nir_src_for_ssa(input_img_deref); + tex->dest_type = nir_type_float; + tex->is_array = false; + tex->coord_components = 1; + nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex"); + nir_builder_instr_insert(&b, &tex->instr); + + nir_ssa_def *outval = &tex->dest.ssa; + + /* dst */ + nir_ssa_def *dst_local_pos = + nir_iadd(&b, dst_global_pos, nir_imm_int(&b, chan)); + + nir_ssa_def *dst_coord = + nir_vec4(&b, dst_local_pos, dst_local_pos, + dst_local_pos, dst_local_pos); + + nir_intrinsic_instr *store = + nir_intrinsic_instr_create(b.shader, + nir_intrinsic_image_deref_store); + store->num_components = 1; + store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa); + store->src[1] = nir_src_for_ssa(dst_coord); + store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); + store->src[3] = nir_src_for_ssa(nir_channel(&b, outval, 0)); + nir_builder_instr_insert(&b, &store->instr); + } + + return b.shader; +} + +/* Image to image - special path for R32G32B32 */ +static VkResult +radv_device_init_meta_itoi_r32g32b32_state(struct radv_device *device) +{ + VkResult result; + struct radv_shader_module cs = { .nir = NULL }; + + cs.nir = build_nir_itoi_r32g32b32_compute_shader(device); + + VkDescriptorSetLayoutCreateInfo ds_create_info = { + .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO, + .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR, + .bindingCount = 2, + .pBindings = (VkDescriptorSetLayoutBinding[]) { + { + .binding = 0, + .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER, + .descriptorCount = 1, + .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT, + .pImmutableSamplers = NULL + }, + { + .binding = 1, + .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER, + .descriptorCount = 1, + .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT, + .pImmutableSamplers = NULL + }, + } + }; + + result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), + &ds_create_info, + &device->meta_state.alloc, + &device->meta_state.itoi_r32g32b32.img_ds_layout); + if (result != VK_SUCCESS) + goto fail; + + + VkPipelineLayoutCreateInfo pl_create_info = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO, + .setLayoutCount = 1, + .pSetLayouts = &device->meta_state.itoi_r32g32b32.img_ds_layout, + .pushConstantRangeCount = 1, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 24}, + }; + + result = radv_CreatePipelineLayout(radv_device_to_handle(device), + &pl_create_info, + &device->meta_state.alloc, + &device->meta_state.itoi_r32g32b32.img_p_layout); + if (result != VK_SUCCESS) + goto fail; + + /* compute shader */ + + VkPipelineShaderStageCreateInfo pipeline_shader_stage = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = radv_shader_module_to_handle(&cs), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo vk_pipeline_info = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = pipeline_shader_stage, + .flags = 0, + .layout = device->meta_state.itoi_r32g32b32.img_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&device->meta_state.cache), + 1, &vk_pipeline_info, NULL, + &device->meta_state.itoi_r32g32b32.pipeline); + +fail: + ralloc_free(cs.nir); + return result; +} + +static void +radv_device_finish_meta_itoi_r32g32b32_state(struct radv_device *device) +{ + struct radv_meta_state *state = &device->meta_state; + + radv_DestroyPipelineLayout(radv_device_to_handle(device), + state->itoi_r32g32b32.img_p_layout, &state->alloc); + radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), + state->itoi_r32g32b32.img_ds_layout, + &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->itoi_r32g32b32.pipeline, &state->alloc); +} + static nir_shader * build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d) { @@ -1266,6 +1476,7 @@ radv_device_finish_meta_bufimage_state(struct radv_device *device) radv_device_finish_meta_btoi_state(device); radv_device_finish_meta_btoi_r32g32b32_state(device); radv_device_finish_meta_itoi_state(device); + radv_device_finish_meta_itoi_r32g32b32_state(device); radv_device_finish_meta_cleari_state(device); radv_device_finish_meta_cleari_r32g32b32_state(device); } @@ -1291,6 +1502,10 @@ radv_device_init_meta_bufimage_state(struct radv_device *device) if (result != VK_SUCCESS) goto fail_itoi; + result = radv_device_init_meta_itoi_r32g32b32_state(device); + if (result != VK_SUCCESS) + goto fail_itoi_r32g32b32; + result = radv_device_init_meta_cleari_state(device); if (result != VK_SUCCESS) goto fail_cleari; @@ -1304,6 +1519,8 @@ fail_cleari_r32g32b32: radv_device_finish_meta_cleari_r32g32b32_state(device); fail_cleari: radv_device_finish_meta_cleari_state(device); +fail_itoi_r32g32b32: + radv_device_finish_meta_itoi_r32g32b32_state(device); fail_itoi: radv_device_finish_meta_itoi_state(device); fail_btoi_r32g32b32: @@ -1680,6 +1897,101 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, } } +static void +itoi_r32g32b32_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, + struct radv_buffer_view *src, + struct radv_buffer_view *dst) +{ + struct radv_device *device = cmd_buffer->device; + + radv_meta_push_descriptor_set(cmd_buffer, + VK_PIPELINE_BIND_POINT_COMPUTE, + device->meta_state.itoi_r32g32b32.img_p_layout, + 0, /* set */ + 2, /* descriptorWriteCount */ + (VkWriteDescriptorSet[]) { + { + .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET, + .dstBinding = 0, + .dstArrayElement = 0, + .descriptorCount = 1, + .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER, + .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(src) }, + }, + { + .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET, + .dstBinding = 1, + .dstArrayElement = 0, + .descriptorCount = 1, + .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER, + .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(dst) }, + } + }); +} + +static void +radv_meta_image_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, + struct radv_meta_blit2d_surf *src, + struct radv_meta_blit2d_surf *dst, + unsigned num_rects, + struct radv_meta_blit2d_rect *rects) +{ + VkPipeline pipeline = cmd_buffer->device->meta_state.itoi_r32g32b32.pipeline; + struct radv_device *device = cmd_buffer->device; + struct radv_buffer_view src_view, dst_view; + unsigned src_offset = 0, dst_offset = 0; + unsigned src_stride, dst_stride; + VkBuffer src_buffer, dst_buffer; + + /* 96-bit formats are only compatible to themselves. */ + assert(dst->format == VK_FORMAT_R32G32B32_UINT || + dst->format == VK_FORMAT_R32G32B32_SINT || + dst->format == VK_FORMAT_R32G32B32_SFLOAT); + + /* This special itoi path for R32G32B32 formats will write the linear + * image as a buffer with the same underlying memory. The compute + * shader will copy all components separately using a R32 format. + */ + create_buffer_from_image(cmd_buffer, src, + VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT, + &src_buffer); + create_buffer_from_image(cmd_buffer, dst, + VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT, + &dst_buffer); + + create_bview_for_r32g32b32(cmd_buffer, radv_buffer_from_handle(src_buffer), + src_offset, src->format, &src_view); + create_bview_for_r32g32b32(cmd_buffer, radv_buffer_from_handle(dst_buffer), + dst_offset, dst->format, &dst_view); + itoi_r32g32b32_bind_descriptors(cmd_buffer, &src_view, &dst_view); + + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), + VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); + + src_stride = get_image_stride_for_r32g32b32(cmd_buffer, src); + dst_stride = get_image_stride_for_r32g32b32(cmd_buffer, dst); + + for (unsigned r = 0; r < num_rects; ++r) { + unsigned push_constants[6] = { + rects[r].src_x, + rects[r].src_y, + src_stride, + rects[r].dst_x, + rects[r].dst_y, + dst_stride, + }; + radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.itoi_r32g32b32.img_p_layout, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, + push_constants); + + radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); + } + + radv_DestroyBuffer(radv_device_to_handle(device), src_buffer, NULL); + radv_DestroyBuffer(radv_device_to_handle(device), dst_buffer, NULL); +} + static void itoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src, @@ -1735,6 +2047,14 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_device *device = cmd_buffer->device; struct radv_image_view src_view, dst_view; + if (src->format == VK_FORMAT_R32G32B32_UINT || + src->format == VK_FORMAT_R32G32B32_SINT || + src->format == VK_FORMAT_R32G32B32_SFLOAT) { + radv_meta_image_to_image_cs_r32g32b32(cmd_buffer, src, dst, + num_rects, rects); + return; + } + create_iview(cmd_buffer, src, &src_view); create_iview(cmd_buffer, dst, &dst_view); diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c index 41da302cf84..ddfb5c54673 100644 --- a/src/amd/vulkan/radv_meta_copy.c +++ b/src/amd/vulkan/radv_meta_copy.c @@ -482,10 +482,14 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer, rect.src_y = src_offset_el.y; /* Perform Blit */ - if (cs) + if (cs || + (b_src.format == VK_FORMAT_R32G32B32_UINT || + b_src.format == VK_FORMAT_R32G32B32_SINT || + b_src.format == VK_FORMAT_R32G32B32_SFLOAT)) { radv_meta_image_to_image_cs(cmd_buffer, &b_src, &b_dst, 1, &rect); - else + } else { radv_meta_blit2d(cmd_buffer, &b_src, NULL, &b_dst, 1, &rect); + } b_src.layer++; b_dst.layer++; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 0464fa4a412..e3c0353d668 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -516,6 +516,11 @@ struct radv_meta_state { VkPipeline pipeline; VkPipeline pipeline_3d; } itoi; + struct { + VkPipelineLayout img_p_layout; + VkDescriptorSetLayout img_ds_layout; + VkPipeline pipeline; + } itoi_r32g32b32; struct { VkPipelineLayout img_p_layout; VkDescriptorSetLayout img_ds_layout; -- 2.30.2