From 79d63479eab35cf9bbb94b44a42c61e056cd9bcd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 13:30:35 -0700 Subject: [PATCH] Improve A/B reg packing --- passes/pmgen/xilinx_dsp.cc | 3 +++ passes/pmgen/xilinx_dsp.pmg | 14 ++++++++------ 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 0010edf55..b583988c4 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -23,6 +23,9 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +template bool includes(const T &lhs, const T &rhs) { + return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end()); +} #include "passes/pmgen/xilinx_dsp_pm.h" void pack_xilinx_dsp(xilinx_dsp_pm &pm) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 51fd733d4..fe907b298 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -9,10 +9,9 @@ endmatch match ffA select ffA->type.in($dff, $dffe) - select param(ffA, \CLK_POLARITY).as_bool() - // select nusers(port(ffA, \Q)) == 2 - index > port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool() // DSP48E1 does not support clock inversion + select param(ffA, \CLK_POLARITY).as_bool() + filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set()) optional endmatch @@ -23,9 +22,9 @@ endcode match ffB select ffB->type.in($dff, $dffe) + // DSP48E1 does not support clock inversion select param(ffB, \CLK_POLARITY).as_bool() - // select nusers(port(ffB, \Q)) == 2 - index > port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool() + filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set()) optional endmatch @@ -52,9 +51,10 @@ endcode match ffP select ffP->type.in($dff, $dffe) select nusers(port(ffP, \D)) == 2 + // DSP48E1 does not support clock inversion + select param(ffP, \CLK_POLARITY).as_bool() filter param(ffP, \WIDTH).as_int() == P_WIDTH filter port(ffP, \D) == port(dsp, \P).extract(0, P_WIDTH) - index param(ffP, \CLK_POLARITY) === State::S1 optional endmatch @@ -76,6 +76,8 @@ match ffY if muxP select ffY->type.in($dff, $dffe) select nusers(port(ffY, \D)) == 2 + // DSP48E1 does not support clock inversion + select param(ffY, \CLK_POLARITY).as_bool() index port(ffY, \D) === port(muxP, \Y) endmatch -- 2.30.2