From 79e4f6cff8d8fd7af99b1dfef16d8b5edc5a24a5 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 27 Apr 2020 11:28:03 +0100
Subject: [PATCH] add memory interface requirements section

---
 3d_gpu/architecture/memory_and_cache.mdwn | 28 +++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index ac02a3248..271ab68d9 100644
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -38,6 +38,34 @@ Basic diagram:
 * Memory is the silicon-proven OpenCores [SDRAM|sdram] interface,
   and it is Wishbone compliant.
 
+## Memory Interface Required by LDSTComputationalUnit
+
+See <https://bugs.libre-soc.org/show_bug.cgi?id=216#c26>.  Other signals
+(type of LD/ST: atomic or I/O, type of exception) left out for brevity
+
+Common to LD/ST:
+
+* out: busy
+* in: is_ld
+* in: address
+* in: len (1/2/4/8)
+* in: go_addr
+* in: go_die
+* out: addr_ok (no exception will occur)
+* out: addr_exc (exception type)
+
+LD:
+
+* in: is_ld
+* out: ld_data
+* out: ld_data_ok (to be raised for 1 cycle)
+
+ST:
+
+* in: is_st
+* in: st_data
+* in: go_st (raised for 1 cycle, must complete)
+
 ## Alternative Design Idea
 
 [[alternative-design-idea]]
-- 
2.30.2