From 79eefb0dd2ba75119f3c722f775b9d60d056f8ac Mon Sep 17 00:00:00 2001 From: Pat Haugen Date: Mon, 7 Mar 2011 19:27:09 +0000 Subject: [PATCH] re PR rtl-optimization/47862 (Incorrect code for spilling a vector register) PR target/47862 * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define. * config/rs6000/e500.h (HARD_REGNO_CALLER_SAVE_MODE): Undefine before definition. * testsuite/gcc.target/powerpc/pr47862.c: New. From-SVN: r170748 --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/e500.h | 2 ++ gcc/config/rs6000/rs6000.h | 10 ++++++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/pr47862.c | 19 +++++++++++++++++++ 5 files changed, 43 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr47862.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0b6a15ba0d8..64ff65e3d1a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2011-03-07 Pat Haugen + + PR target/47862 + * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define. + * config/rs6000/e500.h (HARD_REGNO_CALLER_SAVE_MODE): Undefine + before definition. + 2011-03-07 Zdenek Dvorak PR bootstrap/48000 diff --git a/gcc/config/rs6000/e500.h b/gcc/config/rs6000/e500.h index 744f4de4c58..807df0900a5 100644 --- a/gcc/config/rs6000/e500.h +++ b/gcc/config/rs6000/e500.h @@ -47,6 +47,8 @@ } \ } while (0) +/* Override rs6000.h definition. */ +#undef HARD_REGNO_CALLER_SAVE_MODE /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate space for DFmode. Save gprs in the correct mode too. */ #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 98ec24c75eb..49134568b71 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1005,6 +1005,16 @@ extern unsigned rs6000_pointer_size; #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] +/* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate + enough space to account for vectors in FP regs. */ +#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ + (TARGET_VSX \ + && ((MODE) == VOIDmode || VSX_VECTOR_MODE (MODE) \ + || ALTIVEC_VECTOR_MODE (MODE)) \ + && FP_REGNO_P (REGNO) \ + ? V2DFmode \ + : choose_hard_reg_mode ((REGNO), (NREGS), false)) + #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ (((TARGET_32BIT && TARGET_POWERPC64 \ && (GET_MODE_SIZE (MODE) > 4) \ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 04caa838bff..7635092e696 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2011-03-07 Pat Haugen + + PR target/47862 + * gcc.target/powerpc/pr47862.c: New. + 2011-03-07 Jack Howarth PR target/45413 diff --git a/gcc/testsuite/gcc.target/powerpc/pr47862.c b/gcc/testsuite/gcc.target/powerpc/pr47862.c new file mode 100644 index 00000000000..528cace383c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr47862.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler-not "stfd" } } */ + +/* PR 47862: Verify caller-save spill of vectors in FP regs do not use + legacy FP insns, which spill only half the vector. */ +extern vector double dd[15]; + +vector double foo() { + vector double a,b,c,d,e,f,g,h,i,j,k,l,m,n; + + a=dd[1]; b=dd[2]; c=dd[3]; d=dd[4]; e=dd[5]; f=dd[6]; g=dd[7]; h=dd[8]; i=dd[9]; + j=dd[10]; k=dd[11]; l=dd[12]; m=dd[13]; n=dd[14]; + bar(); + return (a+b+c+d+e+f+g+h+i+j+k+l+m+n); +} + -- 2.30.2