From 7a1eed7b1a6f9be05ac9555e662ca79ea2566da2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Apr 2022 11:24:17 +0100 Subject: [PATCH] add a dramsync2x domain as well --- src/ls2.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/ls2.py b/src/ls2.py index 708673b..6bee6d6 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -370,7 +370,12 @@ class DDR3SoC(SoC, Elaboratable): ddrmodule = dram_cls(clk_freq, "1:2") # match DDR3 ASIC P/N #drs = lambda x: x - drs = DomainRenamer("dramsync") + # remap both the sync domain (wherever it occurs) and + # the sync2x domain. technically this should NOT be done. + # it's a bit of a mess. ok: this should be done only + # when dramsync===sync (and dramsync2x===sync2x) + drs = DomainRenamer({"sync": "dramsync", + "sync2x": "dramsync2x"}) if fpga == 'sim': self.ddrphy = FakePHY(module=ddrmodule, -- 2.30.2