From 7a2e33b817dad1b6f1163d7429e833ab8bc0c095 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Wed, 19 Feb 2020 20:10:32 -0500 Subject: [PATCH] targets/nexys4ddr: add ethernet via method instead of inheritance Switch adding LiteETH support to BaseSoc via a method instead of inheritance. This allows further optional peripherals to be added in the future, via additional methods. Signed-off-by: Gabriel Somlo --- litex/boards/targets/nexys4ddr.py | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 79eaa6d0..61f6bfa2 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -66,18 +66,12 @@ class BaseSoC(SoCSDRAM): geom_settings = sdram_module.geom_settings, timing_settings = sdram_module.timing_settings) -# EthernetSoC -------------------------------------------------------------------------------------- + def add_ethernet(self): + mem_map = { + "ethmac": 0xb0000000, + } + mem_map.update(self.mem_map) -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - - # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYRMII( clock_pads = self.platform.request("eth_clocks"), @@ -113,8 +107,9 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) + if args.with_ethernet: + soc.add_ethernet() builder = Builder(soc, **builder_argdict(args)) builder.build() -- 2.30.2