From 7a38df19fd3e701eb4dda937aa54eb2dfb298053 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Tue, 17 Jul 2001 10:29:18 +0000 Subject: [PATCH] mips.h: Change TUNE_MIPS* options to use mips_tune. 2001-07-16 Eric Christopher * config/mips/mips.h: Change TUNE_MIPS* options to use mips_tune. (EXTRA_SPECS): Add cc1_cpu_spec. * config/mips/mips.md (muldf3): Fix typo. From-SVN: r44068 --- gcc/ChangeLog | 7 +++ gcc/config/mips/mips.h | 11 ++-- gcc/config/mips/mips.md | 118 ++++++++++++++++++++-------------------- 3 files changed, 72 insertions(+), 64 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c704023f6b0..e85b9704558 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2001-07-13 Eric Christopher + + * config/mips/mips.h: Change TUNE_MIPS* options to use + mips_tune. + (EXTRA_SPECS): Add cc1_cpu_spec. + * config/mips/mips.md (muldf3): Fix typo. + 2001-07-16 Richard Henderson * config/m68k/m68k.c: Include expr.h and reload.h. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index b4a912942e5..31dceca3b09 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -337,11 +337,11 @@ extern void sbss_section PARAMS ((void)); #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300) /* Scheduling target defines. */ -#define TUNE_MIPS3000 (mips_cpu == PROCESSOR_R3000) -#define TUNE_MIPS3900 (mips_cpu == PROCESSOR_R3900) -#define TUNE_MIPS4000 (mips_cpu == PROCESSOR_R4000) -#define TUNE_MIPS5000 (mips_cpu == PROCESSOR_R5000) -#define TUNE_MIPS6000 (mips_cpu == PROCESSOR_R6000) +#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) +#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) +#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) +#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) +#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, @@ -1027,6 +1027,7 @@ while (0) #define EXTRA_SPECS \ { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ + { "cc1_cpu_spec", CC1_CPU_SPEC}, \ { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \ { "long_max_spec", LONG_MAX_SPEC }, \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d4649101fa6..a7636f8d316 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -98,7 +98,7 @@ ;; instruction which allows full access to the entire address space, ;; but we do not do so at present. -(define_attr "length" "" +(define_attr "length" "" (cond [(eq_attr "type" "branch") (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4)))) (const_int 131072)) @@ -124,7 +124,7 @@ ;; Does the instruction have a mandatory delay slot? ;; The 3900, is (mostly) mips1, but does not have a mandatory load delay -;; slot. +;; slot. (define_attr "dslot" "no,yes" (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp") (and (eq_attr "type" "load") @@ -496,24 +496,24 @@ ;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0) ;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) -;; +;; ;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0) -;; +;; ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0) ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0) -;; +;; ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0) ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0) -;; +;; ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0) ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0) -;; +;; ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0) ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0) -;; +;; ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0) ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0) -;; +;; ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0) ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0) @@ -1604,7 +1604,7 @@ (const_int 4) (const_int 8)) (const_int 4)])]) - + ;; @@ -1626,7 +1626,7 @@ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" " { - if (TARGET_MIPS4300) + if (!TARGET_MIPS4300) emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2])); else emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2])); @@ -1890,7 +1890,7 @@ { if (GENERATE_MULT3) output_asm_insn (\"dmult\\t%0,%1,%2\", operands); - else + else { rtx xoperands[10]; @@ -2168,7 +2168,7 @@ (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")) (match_operand:SF 3 "register_operand" "f")))] - + "ISA_HAS_FP4 && TARGET_HARD_FLOAT" "msub.s\\t%0,%3,%1,%2" [(set_attr "type" "fmadd") @@ -2304,7 +2304,7 @@ (BITMASK_HIGH, SImode))), GEN_INT (0x6))); } - + DONE; }") @@ -2352,7 +2352,7 @@ GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } - + DONE; }") @@ -2390,7 +2390,7 @@ GEN_INT (0), GEN_INT (0x7))); } - + DONE; }") @@ -2428,7 +2428,7 @@ GEN_INT (0), GEN_INT (0x7))); } - + DONE; }") @@ -2527,7 +2527,7 @@ have_dep_anti = 1; if (! have_dep_anti) { - /* No branch delay slots on mips16. */ + /* No branch delay slots on mips16. */ if (which_alternative == 1) return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\"; else @@ -2566,7 +2566,7 @@ (BITMASK_HIGH, SImode))), GEN_INT (0x6))); } - + DONE; }") @@ -2584,7 +2584,7 @@ (define_expand "divdi3" [(set (match_operand:DI 0 "register_operand" "=l") (div:DI (match_operand:DI 1 "se_register_operand" "d") - (match_operand:DI 2 "se_register_operand" "d"))) + (match_operand:DI 2 "se_register_operand" "d"))) (clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 4 "=a"))] "TARGET_64BIT && !optimize" @@ -2607,7 +2607,7 @@ GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } - + DONE; }") @@ -2650,7 +2650,7 @@ (BITMASK_HIGH, SImode))), GEN_INT (0x6))); } - + DONE; }") @@ -2691,7 +2691,7 @@ GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } - + DONE; }") @@ -2722,7 +2722,7 @@ GEN_INT (0), GEN_INT (0x7))); } - + DONE; }") @@ -2753,7 +2753,7 @@ GEN_INT (0), GEN_INT (0x7))); } - + DONE; }") @@ -2784,7 +2784,7 @@ GEN_INT (0), GEN_INT (0x7))); } - + DONE; }") @@ -2815,7 +2815,7 @@ GEN_INT (0), GEN_INT (0x7))); } - + DONE; }") @@ -2898,7 +2898,7 @@ return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\"; else return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n%~1:\"; - } + } else return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\"; }" @@ -2916,10 +2916,10 @@ dslots_jump_total++; dslots_jump_filled++; operands[2] = const0_rtx; - + if (GET_CODE (operands[1]) == REG) regno1 = REGNO (operands[1]); - else + else regno1 = REGNO (XEXP (operands[1], 0)); if (REGNO (operands[0]) == regno1) @@ -3568,7 +3568,7 @@ move\\t%0,%z4\\n\\ { if (TARGET_MIPS16) return \"dsll\\t%0,%1,56\;dsra\\t%0,56\"; - return \"andi\\t%0,%1,0x00ff\"; + return \"andi\\t%0,%1,0x00ff\"; }" [(set_attr "type" "darith") (set_attr "mode" "QI") @@ -3600,7 +3600,7 @@ move\\t%0,%z4\\n\\ [(set_attr "type" "darith") (set_attr "mode" "SI") (set_attr "length" "8")]) - + (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d") @@ -4522,7 +4522,7 @@ move\\t%0,%z4\\n\\ " { /* If the field does not start on a byte boundary, then fail. */ - if (INTVAL (operands[3]) % 8 != 0) + if (INTVAL (operands[3]) % 8 != 0) FAIL; /* MIPS I and MIPS II can only handle a 32bit field. */ @@ -4570,7 +4570,7 @@ move\\t%0,%z4\\n\\ " { /* If the field does not start on a byte boundary, then fail. */ - if (INTVAL (operands[3]) % 8 != 0) + if (INTVAL (operands[3]) % 8 != 0) FAIL; /* MIPS I and MIPS II can only handle a 32bit field. */ @@ -4618,7 +4618,7 @@ move\\t%0,%z4\\n\\ " { /* If the field does not start on a byte boundary, then fail. */ - if (INTVAL (operands[2]) % 8 != 0) + if (INTVAL (operands[2]) % 8 != 0) FAIL; /* MIPS I and MIPS II can only handle a 32bit field. */ @@ -5056,7 +5056,7 @@ move\\t%0,%z4\\n\\ " { rtx scratch = gen_rtx_REG (DImode, - (REGNO (operands[0]) == REGNO (operands[2]) + (REGNO (operands[0]) == REGNO (operands[2]) ? REGNO (operands[2]) + 1 : REGNO (operands[2]))); @@ -6496,7 +6496,7 @@ move\\t%0,%z4\\n\\ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_operand:SI 3 "register_operand" "=d"))] "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" - "* + "* { operands[4] = const0_rtx; dslots_jump_total += 3; @@ -6854,7 +6854,7 @@ move\\t%0,%z4\\n\\ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_operand:SI 3 "register_operand" "=d"))] "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" - "* + "* { operands[4] = const0_rtx; dslots_jump_total += 3; @@ -7235,7 +7235,7 @@ move\\t%0,%z4\\n\\ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_operand:SI 3 "register_operand" "=d"))] "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" - "* + "* { operands[4] = const0_rtx; dslots_jump_total += 3; @@ -7590,7 +7590,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_fp" [(set (pc) - (if_then_else + (if_then_else (match_operator:CC 0 "cmp_op" [(match_operand:CC 2 "register_operand" "z") (const_int 0)]) @@ -7611,7 +7611,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_fp_inverted" [(set (pc) - (if_then_else + (if_then_else (match_operator:CC 0 "cmp_op" [(match_operand:CC 2 "register_operand" "z") (const_int 0)]) @@ -7634,7 +7634,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_zero" [(set (pc) - (if_then_else + (if_then_else (match_operator:SI 0 "cmp_op" [(match_operand:SI 2 "register_operand" "d") (const_int 0)]) @@ -7655,7 +7655,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_zero_inverted" [(set (pc) - (if_then_else + (if_then_else (match_operator:SI 0 "cmp_op" [(match_operand:SI 2 "register_operand" "d") (const_int 0)]) @@ -7676,7 +7676,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_zero_di" [(set (pc) - (if_then_else + (if_then_else (match_operator:DI 0 "cmp_op" [(match_operand:DI 2 "se_register_operand" "d") (const_int 0)]) @@ -7697,7 +7697,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_zero_di_inverted" [(set (pc) - (if_then_else + (if_then_else (match_operator:DI 0 "cmp_op" [(match_operand:DI 2 "se_register_operand" "d") (const_int 0)]) @@ -7720,7 +7720,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_equality" [(set (pc) - (if_then_else + (if_then_else (match_operator:SI 0 "equality_op" [(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d")]) @@ -7741,7 +7741,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_equality_di" [(set (pc) - (if_then_else + (if_then_else (match_operator:DI 0 "equality_op" [(match_operand:DI 2 "se_register_operand" "d") (match_operand:DI 3 "se_register_operand" "d")]) @@ -7762,7 +7762,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_equality_inverted" [(set (pc) - (if_then_else + (if_then_else (match_operator:SI 0 "equality_op" [(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d")]) @@ -7783,7 +7783,7 @@ move\\t%0,%z4\\n\\ (define_insn "branch_equality_di_inverted" [(set (pc) - (if_then_else + (if_then_else (match_operator:DI 0 "equality_op" [(match_operand:DI 2 "se_register_operand" "d") (match_operand:DI 3 "se_register_operand" "d")]) @@ -9061,7 +9061,7 @@ move\\t%0,%z4\\n\\ in a switch table, then used in a `j' instruction. */ else if (mips_abi != ABI_32 && mips_abi != ABI_O64) return \"%*b\\t%l0\"; - else + else return \"%*j\\t%l0\"; }" [(set_attr "type" "jump") @@ -9313,10 +9313,10 @@ move\\t%0,%z4\\n\\ /* Do the PIC jump. */ if (Pmode != DImode) - emit_jump_insn (gen_casesi_internal (reg, operands[3], + emit_jump_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode))); else - emit_jump_insn (gen_casesi_internal_di (reg, operands[3], + emit_jump_insn (gen_casesi_internal_di (reg, operands[3], gen_reg_rtx (DImode))); DONE; @@ -9352,7 +9352,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (define_insn "casesi_internal_di" [(set (pc) - (mem:DI (plus:DI (sign_extend:DI + (mem:DI (plus:DI (sign_extend:DI (mult:SI (match_operand:SI 0 "register_operand" "d") (const_int 4))) (label_ref (match_operand 1 "" ""))))) @@ -9396,7 +9396,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" "TARGET_ABICALLS && Pmode == DImode" "") -;; For o32/n32/n64, we need to arrange for longjmp to put the +;; For o32/n32/n64, we need to arrange for longjmp to put the ;; target address in t9 so that we can use it for loading $gp. (define_expand "builtin_longjmp" @@ -9490,7 +9490,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" }" [(set_attr "type" "jump") (set_attr "mode" "none")]) - + ;; When generating embedded PIC code we need to get the address of the ;; current function. This specialized instruction does just that. @@ -9934,7 +9934,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (call (mem:SI (match_operand:SI 1 "register_operand" "r")) (match_operand 2 "" "i"))) (clobber (match_operand:SI 3 "register_operand" "=d"))] - "!TARGET_MIPS16 + "!TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS" "%*jal\\t%3,%1" [(set_attr "type" "call") @@ -9945,7 +9945,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (call (mem:DI (match_operand:DI 1 "se_register_operand" "r")) (match_operand 2 "" "i"))) (clobber (match_operand:SI 3 "register_operand" "=d"))] - "!TARGET_MIPS16 + "!TARGET_MIPS16 && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS" "%*jal\\t%3,%1" [(set_attr "type" "call") @@ -10118,7 +10118,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" ;; operands[0] = gen_reg_rtx (SImode); ;; operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx); ;; MEM_VOLATILE_P (operands[1]) = TRUE; -;; +;; ;; /* fall through and generate default code */ ;; }") ;; @@ -10331,7 +10331,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (if_then_else:DI (match_dup 5) (match_operand:DI 2 "se_reg_or_0_operand" "") (match_operand:DI 3 "se_reg_or_0_operand" "")))] - "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" " { gen_conditional_move (operands); -- 2.30.2