From 7a45122168d06a416f1341e1adf0760cc4c462b8 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 14 Jan 2019 16:08:58 +0000 Subject: [PATCH] manual: explain $tribuf cell. --- manual/CHAPTER_CellLib.tex | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index e22664a82..464f7d1a9 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -119,6 +119,12 @@ than one bit from \B{S} is set the output is undefined. Cells of this type are u ``parallel cases'' (defined by using the {\tt parallel\_case} attribute or detected by an optimization). +The {\tt \$tribuf} cell is used to implement tristate logic. Cells of this type have a \B{WIDTH} +parameter and inputs \B{A} and \B{EN} and an output \B{Y}. The \B{A} input and \B{Y} output are +\B{WIDTH} bits wide, and the \B{EN} input is one bit wide. When \B{EN} is 0, the output \B{Y} +is not driven. When \B{EN} is 1, the value from \B{A} input is sent to the \B{Y} output. Therefore, +the {\tt \$tribuf} cell implements the function \lstinline[language=Verilog]; Y = EN ? A : 'bz;. + Behavioural code with cascaded {\tt if-then-else}- and {\tt case}-statements usually results in trees of multiplexer cells. Many passes (from various optimizations to FSM extraction) heavily depend on these multiplexer trees to @@ -476,6 +482,10 @@ Add information about {\tt \$dffe}, {\tt \$dffsr}, {\tt \$dlatch}, and {\tt \$dl Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells. \end{fixme} +\begin{fixme} +Add information about {\tt \$\_TBUF\_} cells. +\end{fixme} + \begin{fixme} Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_ANDNOT\_}, {\tt \$\_ORNOT\_}, {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells. -- 2.30.2