From 7a6588fe65432c0f1a8b5fdefba81700ebf88711 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 7 Apr 2020 10:01:16 +0200 Subject: [PATCH] aarch64: Fix {ash[lr],lshr}3 expanders [PR94488] The following testcase ICEs on aarch64 apparently since the introduction of the aarch64 port. The reason is that the {ashl,ashr,lshr}3 expanders completely unnecessarily FAIL; if operands[2] is something other than a CONST_INT or REG or MEM and the middle-end code can't cope with the pattern giving up in these cases. All the expanders use general_operand predicate for the shift amount operand, but then have just a special case for CONST_INT (if in-bound, emit an immediate shift, otherwise force into REG), or MEM (force into REG), or REG (that is the case it handles). In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid general_operand. I don't see any reason what is magic about MEMs that it should be forced into REG and others like SUBREGs that it shouldn't, there isn't even a reason to check for !REG_P because force_reg will do nothing if the operand is already a REG, and otherwise can handle general_operand just fine. 2020-04-07 Jakub Jelinek PR target/94488 * config/aarch64/aarch64-simd.md (ashl3, lshr3, ashr3): Force operands[2] into reg whenever it is not CONST_INT. Assume it is a REG after that instead of testing it and doing FAIL otherwise. Formatting fix. * gcc.c-torture/compile/pr94488.c: New test. --- gcc/config/aarch64/aarch64-simd.md | 100 ++++++------------ gcc/testsuite/gcc.c-torture/compile/pr94488.c | 22 ++++ 2 files changed, 53 insertions(+), 69 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94488.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 24a11fb5040..9f0e2bd1e6f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1105,31 +1105,17 @@ tmp)); DONE; } - else - { - operands[2] = force_reg (SImode, operands[2]); - } - } - else if (MEM_P (operands[2])) - { - operands[2] = force_reg (SImode, operands[2]); } - if (REG_P (operands[2])) - { - rtx tmp = gen_reg_rtx (mode); - emit_insn (gen_aarch64_simd_dup (tmp, - convert_to_mode (mode, - operands[2], - 0))); - emit_insn (gen_aarch64_simd_reg_sshl (operands[0], operands[1], - tmp)); - DONE; - } - else - FAIL; -} -) + operands[2] = force_reg (SImode, operands[2]); + + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_aarch64_simd_dup (tmp, convert_to_mode (mode, + operands[2], + 0))); + emit_insn (gen_aarch64_simd_reg_sshl (operands[0], operands[1], tmp)); + DONE; +}) (define_expand "lshr3" [(match_operand:VDQ_I 0 "register_operand") @@ -1152,31 +1138,19 @@ tmp)); DONE; } - else - operands[2] = force_reg (SImode, operands[2]); - } - else if (MEM_P (operands[2])) - { - operands[2] = force_reg (SImode, operands[2]); } - if (REG_P (operands[2])) - { - rtx tmp = gen_reg_rtx (SImode); - rtx tmp1 = gen_reg_rtx (mode); - emit_insn (gen_negsi2 (tmp, operands[2])); - emit_insn (gen_aarch64_simd_dup (tmp1, - convert_to_mode (mode, - tmp, 0))); - emit_insn (gen_aarch64_simd_reg_shl_unsigned (operands[0], - operands[1], - tmp1)); - DONE; - } - else - FAIL; -} -) + operands[2] = force_reg (SImode, operands[2]); + + rtx tmp = gen_reg_rtx (SImode); + rtx tmp1 = gen_reg_rtx (mode); + emit_insn (gen_negsi2 (tmp, operands[2])); + emit_insn (gen_aarch64_simd_dup (tmp1, + convert_to_mode (mode, tmp, 0))); + emit_insn (gen_aarch64_simd_reg_shl_unsigned (operands[0], operands[1], + tmp1)); + DONE; +}) (define_expand "ashr3" [(match_operand:VDQ_I 0 "register_operand") @@ -1199,31 +1173,19 @@ tmp)); DONE; } - else - operands[2] = force_reg (SImode, operands[2]); - } - else if (MEM_P (operands[2])) - { - operands[2] = force_reg (SImode, operands[2]); } - if (REG_P (operands[2])) - { - rtx tmp = gen_reg_rtx (SImode); - rtx tmp1 = gen_reg_rtx (mode); - emit_insn (gen_negsi2 (tmp, operands[2])); - emit_insn (gen_aarch64_simd_dup (tmp1, - convert_to_mode (mode, - tmp, 0))); - emit_insn (gen_aarch64_simd_reg_shl_signed (operands[0], - operands[1], - tmp1)); - DONE; - } - else - FAIL; -} -) + operands[2] = force_reg (SImode, operands[2]); + + rtx tmp = gen_reg_rtx (SImode); + rtx tmp1 = gen_reg_rtx (mode); + emit_insn (gen_negsi2 (tmp, operands[2])); + emit_insn (gen_aarch64_simd_dup (tmp1, convert_to_mode (mode, + tmp, 0))); + emit_insn (gen_aarch64_simd_reg_shl_signed (operands[0], operands[1], + tmp1)); + DONE; +}) (define_expand "vashl3" [(match_operand:VDQ_I 0 "register_operand") diff --git a/gcc/testsuite/gcc.c-torture/compile/pr94488.c b/gcc/testsuite/gcc.c-torture/compile/pr94488.c new file mode 100644 index 00000000000..6e20a4168de --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr94488.c @@ -0,0 +1,22 @@ +/* PR target/94488 */ + +typedef unsigned long V __attribute__((__vector_size__(16))); +typedef long W __attribute__((__vector_size__(16))); + +void +foo (V *x, unsigned long y) +{ + *x = *x >> (unsigned int) y; +} + +void +bar (V *x, unsigned long y) +{ + *x = *x << (unsigned int) y; +} + +void +baz (W *x, unsigned long y) +{ + *x = *x >> (unsigned int) y; +} -- 2.30.2