From 7a661d95c03541031a7c1799e1262b94efd64330 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 1 Mar 2020 22:38:59 +0000 Subject: [PATCH] managed to hack something together to get alu_hier sub-routed --- experiments5/alu_hier_altered.vst | 495 ++++++++++++++++++++++++++++++ experiments5/ringoscillator.py | 136 ++++++-- 2 files changed, 606 insertions(+), 25 deletions(-) create mode 100644 experiments5/alu_hier_altered.vst diff --git a/experiments5/alu_hier_altered.vst b/experiments5/alu_hier_altered.vst new file mode 100644 index 0000000..2d4ec23 --- /dev/null +++ b/experiments5/alu_hier_altered.vst @@ -0,0 +1,495 @@ + +-- ======================================================================= +-- Coriolis Structural VHDL Driver +-- Generated on Feb 28, 2020, 20:44 +-- +-- To be interoperable with Alliance, it uses it's special VHDL subset. +-- ("man vhdl" under Alliance for more informations) +-- ======================================================================= + +entity alu_hier_altered is + port ( clk : in bit + ; op : in bit + ; rst : in bit + ; a : in bit_vector(15 downto 0) + ; b : in bit_vector(15 downto 0) + ; o : out bit_vector(15 downto 0) + ; vdd : in bit + ; vss : in bit + ); +end alu_hier_altered; + +architecture structural of alu_hier_altered is + + component add + port ( a : in bit_vector(15 downto 0) + ; b : in bit_vector(15 downto 0) + ; o : out bit_vector(15 downto 0) + ; vdd : in bit + ; vss : in bit + ); + end component; + + component no2_x1 + port ( i0 : in bit + ; i1 : in bit + ; nq : out bit + ; vdd : in bit + ; vss : in bit + ); + end component; + + component sub + port ( a : in bit_vector(15 downto 0) + ; b : in bit_vector(15 downto 0) + ; o : out bit_vector(15 downto 0) + ; vdd : in bit + ; vss : in bit + ); + end component; + + component nmx2_x1 + port ( cmd : in bit + ; i0 : in bit + ; i1 : in bit + ; nq : out bit + ; vdd : in bit + ; vss : in bit + ); + end component; + + component sff1_x4 + port ( ck : in bit + ; i : in bit + ; q : out bit + ; vdd : in bit + ; vss : in bit + ); + end component; + + signal abc_828_new_n51 : bit; + signal abc_828_new_n53 : bit; + signal abc_828_new_n55 : bit; + signal abc_828_new_n57 : bit; + signal abc_828_new_n59 : bit; + signal abc_828_new_n61 : bit; + signal abc_828_new_n63 : bit; + signal abc_828_new_n65 : bit; + signal abc_828_new_n67 : bit; + signal abc_828_new_n69 : bit; + signal abc_828_new_n71 : bit; + signal abc_828_new_n73 : bit; + signal abc_828_new_n75 : bit; + signal abc_828_new_n77 : bit; + signal abc_828_new_n79 : bit; + signal abc_828_new_n81 : bit; + signal blockagenet : bit; + signal add_o : bit_vector(15 downto 0); + signal o_next : bit_vector(15 downto 0); + signal sub_o : bit_vector(15 downto 0); + + +begin + + subckt_0_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(0) + , i1 => sub_o(0) + , nq => abc_828_new_n51 + , vdd => vdd + , vss => vss + ); + + subckt_28_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(14) + , i1 => sub_o(14) + , nq => abc_828_new_n79 + , vdd => vdd + , vss => vss + ); + + subckt_31_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n81 + , i1 => rst + , nq => o_next(15) + , vdd => vdd + , vss => vss + ); + + subckt_36_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(4) + , q => o(4) + , vdd => vdd + , vss => vss + ); + + subckt_44_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(12) + , q => o(12) + , vdd => vdd + , vss => vss + ); + + subckt_14_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(7) + , i1 => sub_o(7) + , nq => abc_828_new_n65 + , vdd => vdd + , vss => vss + ); + + subckt_21_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n71 + , i1 => rst + , nq => o_next(10) + , vdd => vdd + , vss => vss + ); + + subckt_22_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(11) + , i1 => sub_o(11) + , nq => abc_828_new_n73 + , vdd => vdd + , vss => vss + ); + + subckt_23_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n73 + , i1 => rst + , nq => o_next(11) + , vdd => vdd + , vss => vss + ); + + subckt_35_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(3) + , q => o(3) + , vdd => vdd + , vss => vss + ); + + subckt_30_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(15) + , i1 => sub_o(15) + , nq => abc_828_new_n81 + , vdd => vdd + , vss => vss + ); + + subckt_29_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n79 + , i1 => rst + , nq => o_next(14) + , vdd => vdd + , vss => vss + ); + + subckt_27_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n77 + , i1 => rst + , nq => o_next(13) + , vdd => vdd + , vss => vss + ); + + subckt_25_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n75 + , i1 => rst + , nq => o_next(12) + , vdd => vdd + , vss => vss + ); + + subckt_4_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(2) + , i1 => sub_o(2) + , nq => abc_828_new_n55 + , vdd => vdd + , vss => vss + ); + + subckt_1_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n51 + , i1 => rst + , nq => o_next(0) + , vdd => vdd + , vss => vss + ); + + subckt_43_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(11) + , q => o(11) + , vdd => vdd + , vss => vss + ); + + subckt_15_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n65 + , i1 => rst + , nq => o_next(7) + , vdd => vdd + , vss => vss + ); + + subckt_18_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(9) + , i1 => sub_o(9) + , nq => abc_828_new_n69 + , vdd => vdd + , vss => vss + ); + + subckt_13_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n63 + , i1 => rst + , nq => o_next(6) + , vdd => vdd + , vss => vss + ); + + subckt_11_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n61 + , i1 => rst + , nq => o_next(5) + , vdd => vdd + , vss => vss + ); + + subckt_3_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n53 + , i1 => rst + , nq => o_next(1) + , vdd => vdd + , vss => vss + ); + + subckt_5_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n55 + , i1 => rst + , nq => o_next(2) + , vdd => vdd + , vss => vss + ); + + subckt_7_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n57 + , i1 => rst + , nq => o_next(3) + , vdd => vdd + , vss => vss + ); + + subckt_26_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(13) + , i1 => sub_o(13) + , nq => abc_828_new_n77 + , vdd => vdd + , vss => vss + ); + + subckt_34_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(2) + , q => o(2) + , vdd => vdd + , vss => vss + ); + + subckt_47_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(15) + , q => o(15) + , vdd => vdd + , vss => vss + ); + + subckt_42_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(10) + , q => o(10) + , vdd => vdd + , vss => vss + ); + + subckt_20_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(10) + , i1 => sub_o(10) + , nq => abc_828_new_n71 + , vdd => vdd + , vss => vss + ); + + subckt_19_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n69 + , i1 => rst + , nq => o_next(9) + , vdd => vdd + , vss => vss + ); + + subckt_17_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n67 + , i1 => rst + , nq => o_next(8) + , vdd => vdd + , vss => vss + ); + + subckt_12_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(6) + , i1 => sub_o(6) + , nq => abc_828_new_n63 + , vdd => vdd + , vss => vss + ); + + subckt_9_no2_x1 : no2_x1 + port map ( i0 => abc_828_new_n59 + , i1 => rst + , nq => o_next(4) + , vdd => vdd + , vss => vss + ); + + subckt_39_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(7) + , q => o(7) + , vdd => vdd + , vss => vss + ); + + subckt_41_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(9) + , q => o(9) + , vdd => vdd + , vss => vss + ); + + subckt_2_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(1) + , i1 => sub_o(1) + , nq => abc_828_new_n53 + , vdd => vdd + , vss => vss + ); + + subckt_8_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(4) + , i1 => sub_o(4) + , nq => abc_828_new_n59 + , vdd => vdd + , vss => vss + ); + + subckt_33_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(1) + , q => o(1) + , vdd => vdd + , vss => vss + ); + + subckt_38_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(6) + , q => o(6) + , vdd => vdd + , vss => vss + ); + + subckt_32_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(0) + , q => o(0) + , vdd => vdd + , vss => vss + ); + + subckt_24_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(12) + , i1 => sub_o(12) + , nq => abc_828_new_n75 + , vdd => vdd + , vss => vss + ); + + subckt_16_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(8) + , i1 => sub_o(8) + , nq => abc_828_new_n67 + , vdd => vdd + , vss => vss + ); + + subckt_46_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(14) + , q => o(14) + , vdd => vdd + , vss => vss + ); + + subckt_40_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(8) + , q => o(8) + , vdd => vdd + , vss => vss + ); + + subckt_37_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(5) + , q => o(5) + , vdd => vdd + , vss => vss + ); + + subckt_10_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(5) + , i1 => sub_o(5) + , nq => abc_828_new_n61 + , vdd => vdd + , vss => vss + ); + + subckt_6_nmx2_x1 : nmx2_x1 + port map ( cmd => op + , i0 => add_o(3) + , i1 => sub_o(3) + , nq => abc_828_new_n57 + , vdd => vdd + , vss => vss + ); + + subckt_45_sff1_x4 : sff1_x4 + port map ( ck => clk + , i => o_next(13) + , q => o(13) + , vdd => vdd + , vss => vss + ); + +end structural; + diff --git a/experiments5/ringoscillator.py b/experiments5/ringoscillator.py index 2550aa0..afa4819 100755 --- a/experiments5/ringoscillator.py +++ b/experiments5/ringoscillator.py @@ -4,6 +4,7 @@ import sys import re import traceback +import shutil import os.path import optparse import Cfg @@ -380,9 +381,9 @@ class Model (object): self.af = CRL.AllianceFramework.get() #self.cell = af.createCell(modelName) if not views: - self.cell = af.getCell( modelName, CRL.Catalog.State.Logical ) + self.cell = self.af.getCell( modelName, CRL.Catalog.State.Logical ) else: - self.cell = af.getCell( modelName, CRL.Catalog.State.Views ) + self.cell = self.af.getCell( modelName, CRL.Catalog.State.Views ) self.createNet('vss', direction=Net.Direction.IN, isExternal=True, isGlobal=True, type=Net.Type.POWER) self.createNet('vdd', direction=Net.Direction.IN, @@ -445,7 +446,7 @@ class Model (object): instance = self.cell.getInstance(instanceName) if not instance: if isinstance(modelRef, str): - model = af.getCell(modelRef, CRL.Catalog.State.Views) + model = self.af.getCell(modelRef, CRL.Catalog.State.Views) else: model = modelRef instance = Instance.create(self.cell, instanceName, model) @@ -634,6 +635,7 @@ class Ringed (Model): METAL1 = self.getLayer("METAL1") METAL2 = self.getLayer("METAL2") METAL3 = self.getLayer("METAL3") + METAL4 = self.getLayer("METAL3") VIA12 = self.getLayer("VIA12") VIA23 = self.getLayer("VIA23") powerWidth = toDbU(2.0) @@ -678,8 +680,11 @@ class Ringed (Model): westContactsVdd.insert(-1, westContact) eastContactsVdd.insert(-1, eastContact) - self.createVertical(westContactsVdd, vddAxis.getXMin(), powerWidth) - self.createVertical(eastContactsVdd, vddAxis.getXMax(), powerWidth) + for layer in [METAL2, METAL3]: + self.createVertical(westContactsVdd, vddAxis.getXMin(), powerWidth, + layer=layer) + self.createVertical(eastContactsVdd, vddAxis.getXMax(), powerWidth, + layer=layer) xcenter = vddAxis.getCenter().getX() + powerWidth / 2 + toDbU(5.0) if False: @@ -769,8 +774,11 @@ class Ringed (Model): westContactsVss.insert(-1, westContact) eastContactsVss.insert(-1, eastContact) - self.createVertical(westContactsVss, vssAxis.getXMin(), powerWidth) - self.createVertical(eastContactsVss, vssAxis.getXMax(), powerWidth) + for layer in [METAL2, METAL3]: + self.createVertical(westContactsVss, vssAxis.getXMin(), powerWidth, + layer=layer) + self.createVertical(eastContactsVss, vssAxis.getXMax(), powerWidth, + layer=layer) xcenter = vssAxis.getCenter().getX() - powerWidth / 2 - toDbU(5.0) if False: @@ -843,9 +851,9 @@ class AddSubPlace(Ringed): metal2 = DataBase.getDB().getTechnology().getLayer( 'metal2' ) metal3 = DataBase.getDB().getTechnology().getLayer( 'metal3' ) - add = af.getCell( 'add', CRL.Catalog.State.Views ) - sub = af.getCell( 'sub', CRL.Catalog.State.Views ) - #cell = af.getCell( 'alu_hier', CRL.Catalog.State.Logical ) + add = self.af.getCell( 'add', CRL.Catalog.State.Views ) + sub = self.af.getCell( 'sub', CRL.Catalog.State.Views ) + #cell = self.af.getCell( 'alu_hier', CRL.Catalog.State.Logical ) if not cell: print '[ERROR] Unable to load cell "snx.vst", aborting .' return False @@ -853,17 +861,17 @@ class AddSubPlace(Ringed): ab = Box( l( 0.0 ) , l( 0.0 ) - , l( 900.0 ) - , l( 600.0 ) ) + , l( 850.0 ) + , l( 700.0 ) ) #UpdateSession.open() cell.setAbutmentBox( ab ) - transf = (l(50.0), l(100.0), Transformation.Orientation.ID) + transf = (l(25.0), l(250.0), Transformation.Orientation.ID) subi = self.createInstance("subckt_49_sub", sub, transf=transf) print "sub place", subi - transf = (l(500.0), l(100.0), Transformation.Orientation.ID) + transf = (l(450.0), l(250.0), Transformation.Orientation.ID) addi = self.createInstance("subckt_48_add", add, transf=transf) print "add place", addi @@ -910,12 +918,60 @@ class AddSubPlace(Ringed): print "editor", editor, dir(editor) - #af.saveCell( cell, CRL.Catalog.State.Views ) + #self.af.saveCell( cell, CRL.Catalog.State.Views ) #plugins.RSavePlugin.ScriptMain( **kw ) return 0 +class AddSubEtesian(Ringed): + + def build(self): + self.alu_hier_route() + + def alu_hier_route(self, **kw): + + cell = self.cell + editor = None + if kw.has_key('editor') and kw['editor']: + editor = kw['editor'] + + db = DataBase.getDB() + print db, dir(db) + metal2 = DataBase.getDB().getTechnology().getLayer( 'metal2' ) + metal3 = DataBase.getDB().getTechnology().getLayer( 'metal3' ) + + #cell = self.af.getCell( 'alu_hier', CRL.Catalog.State.Logical ) + if not cell: + print '[ERROR] Unable to load cell "snx.vst", aborting .' + return False + kw[ 'cell' ] = cell + + ab = Box( l( 0.0 ) + , l( 0.0 ) + , l( 850.0 ) + , l( 175.0 ) ) + + cell.setAbutmentBox( ab ) + + if editor: editor.setCell( cell ) + + print "editor", editor, dir(editor) + + success = 0 + + etesian = Etesian.EtesianEngine.create(cell) + etesian.place() + + print "cell", cell, dir(cell) + c = cell.getComponents() + print "components", c, dir(c) + for child in cell.getInstances(): + print "child", child + + return success + + class AddSubRoute(Ringed): def build(self): @@ -933,7 +989,7 @@ class AddSubRoute(Ringed): metal2 = DataBase.getDB().getTechnology().getLayer( 'metal2' ) metal3 = DataBase.getDB().getTechnology().getLayer( 'metal3' ) - #cell = af.getCell( 'alu_hier', CRL.Catalog.State.Logical ) + #cell = self.af.getCell( 'alu_hier', CRL.Catalog.State.Logical ) if not cell: print '[ERROR] Unable to load cell "snx.vst", aborting .' return False @@ -941,8 +997,8 @@ class AddSubRoute(Ringed): ab = Box( l( 0.0 ) , l( 0.0 ) - , l( 900.0 ) - , l( 600.0 ) ) + , l( 850.0 ) + , l( 700.0 ) ) cell.setAbutmentBox( ab ) @@ -950,10 +1006,9 @@ class AddSubRoute(Ringed): print "editor", editor, dir(editor) - if True: - etesian = Etesian.EtesianEngine.create(cell) - #etesian.place() + success = 0 + if True: katana = Katana.KatanaEngine.create(cell) katana.digitalInit () katana.runNegociatePreRouted() @@ -966,10 +1021,9 @@ class AddSubRoute(Ringed): print dir(katana) success = katana.getSuccessState() katana.destroy() - else: success = 0 - #af.saveCell( cell, CRL.Catalog.State.Views ) + #self.af.saveCell( cell, CRL.Catalog.State.Views ) #plugins.RSavePlugin.ScriptMain( **kw ) print "cell", cell, dir(cell) @@ -991,9 +1045,41 @@ def ScriptMain(**kw): add.save() sub = Sub('sub') sub.save() - addsub = AddSubPlace('alu_hier') + # create blank ap + print ("Create alu_hier.ap") + cell = af.getCell( "alu_hier", CRL.Catalog.State.Views ) + plugins.RSavePlugin.ScriptMain( cell=cell ) + + print ("copying alu_hier to altered") + with open("alu_hier.ap") as f: + x = f.read() + x = x.replace("alu_hier", "alu_hier_altered") + with open("alu_hier_altered.ap", "w") as f: + f.write(x) + + print ("AddSubEtesian") + addsub = AddSubEtesian('alu_hier_altered', True, True) addsub.save() - addsub = AddSubRoute('alu_hier', False, True) + + print ("copying altered to alu_hier ") + with open("alu_hier_altered.ap") as f: + x = f.read() + x = x.replace("alu_hier_altered", "alu_hier_altered2") + with open("alu_hier_altered2.ap", "w") as f: + f.write(x) + + with open("alu_hier.vst") as f: + x = f.read() + x = x.replace("alu_hier", "alu_hier_altered2") + with open("alu_hier_altered2.vst", "w") as f: + f.write(x) + + print ("AddSubPlace") + addsub = AddSubPlace('alu_hier_altered2', True, True) + addsub.save() + + print ("AddSubRoute") + addsub = AddSubRoute('alu_hier_altered2', True, True) addsub.save() #if editor: -- 2.30.2