From 7a70f5b14f016f704b1c0a7326fae5ebacd54b28 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 23 Aug 2020 22:07:33 +0100 Subject: [PATCH] update copyright notices to include additional primary author (michael, please make sure to be properly informed on copyright law. the git commit logs are the "ultimate" record, and simply being just one of the authors does not mean that you can take the entire code and re-license it under your own license. you can only take the portions that *you* wrote) --- src/soc/decoder/power_decoder.py | 7 +++++-- src/soc/fu/branch/main_stage.py | 5 ++++- src/soc/fu/cr/main_stage.py | 5 ++++- src/soc/fu/shift_rot/main_stage.py | 5 ++++- src/soc/simulator/gas.py | 5 ++++- src/soc/simulator/program.py | 5 ++++- 6 files changed, 25 insertions(+), 7 deletions(-) diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py index 01af7352..e4b87db1 100644 --- a/src/soc/decoder/power_decoder.py +++ b/src/soc/decoder/power_decoder.py @@ -1,5 +1,10 @@ """Cascading Power ISA Decoder +License: LGPLv3 + +# Copyright (C) 2020 Luke Kenneth Casson Leighton +# Copyright (C) 2020 Michael Nolan + This module uses CSV tables in a hierarchical/peer cascading fashion, to create a multi-level instruction decoder by recognising appropriate patterns. The output is a wide, flattened (1-level) series of bitfields, @@ -78,8 +83,6 @@ Top Level: ] -Copyrights: -# Copyright (C) 2020 Michael Nolan """ from collections import namedtuple diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py index 8a1b5f0b..a8caa144 100644 --- a/src/soc/fu/branch/main_stage.py +++ b/src/soc/fu/branch/main_stage.py @@ -1,3 +1,7 @@ +# License: LGPLv3 +# Copyright (C) 2020 Luke Kenneth Casson Leighton +# Copyright (C) 2020 Michael Nolan + """Branch Pipeline This stage is intended to do most of the work of executing branch @@ -23,7 +27,6 @@ Links: * https://bugs.libre-soc.org/show_bug.cgi?id=335 * https://libre-soc.org/openpower/isa/branch/ """ -# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index 36f587eb..ac16f989 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -1,3 +1,7 @@ +# License: LGPLv3 +# Copyright (C) 2020 Michael Nolan +# Copyright (C) 2020 Luke Kenneth Casson Leighton + # This stage is intended to do Condition Register instructions (and ISEL) # and output, as well as carry and overflow generation. # NOTE: with the exception of mtcrf and mfcr, we really should be doing @@ -8,7 +12,6 @@ # own "Register File" (indexed by bt, ba and bb), # exactly how INT regs are done (by RA, RB, RS and RT) # however we are pushed for time so do it as *one* register. -# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index 7d9dad09..c0459874 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -1,8 +1,11 @@ +# License: LGPLv3 +# Copyright (C) 2020 Michael Nolan +# Copyright (C) 2020 Luke Kenneth Casson Leighton + # This stage is intended to do most of the work of executing shift # instructions, as well as carry and overflow generation. This module # however should not gate the carry or overflow, that's up to the # output stage -# Copyright (C) 2020 Michael Nolan from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase from soc.fu.logical.pipe_data import LogicalOutputData diff --git a/src/soc/simulator/gas.py b/src/soc/simulator/gas.py index 14b2cd2c..5e36a14f 100644 --- a/src/soc/simulator/gas.py +++ b/src/soc/simulator/gas.py @@ -1,7 +1,10 @@ +# License: LPGLv3 +# Copyright (C) 2020 Michael Nolan +# Copyright (C) 2020 Luke Kenneth Casson Leighton + import tempfile import subprocess import struct -# Copyright (C) 2020 Michael Nolan def get_assembled_instruction(instruction, bigendian=False): diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py index 86cbf6b3..aeb33a23 100644 --- a/src/soc/simulator/program.py +++ b/src/soc/simulator/program.py @@ -1,9 +1,12 @@ +# License: LGPLv3 +# Copyright (C) 2020 Michael Nolan +# Copyright (C) 2020 Luke Kenneth Casson Leighton + """POWER Program takes powerpc assembly instructions and turns them into LE/BE binary data. calls powerpc64-linux-gnu-as, ld and objcopy to do so. """ -# Copyright (C) 2020 Michael Nolan import tempfile import subprocess -- 2.30.2