From 7a79843cc394f59bdd40473a823c7f60c87d3fa6 Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Wed, 15 Jul 2020 11:54:28 +0200 Subject: [PATCH] Use %precedence in verilog_parser.y Signed-off-by: Claire Wolf --- frontends/verilog/verilog_parser.y | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 390ef07e9..63f0341d9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -299,14 +299,14 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %left '+' '-' %left '*' '/' '%' %left OP_POW -%left OP_CAST -%right UNARY_OPS +%precedence OP_CAST +%precedence UNARY_OPS %define parse.error verbose %define parse.lac full -%nonassoc FAKE_THEN -%nonassoc TOK_ELSE +%precedence FAKE_THEN +%precedence TOK_ELSE %debug %locations -- 2.30.2