From 7a8c24d52a450382855fc6e9d108c344320be7a1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 3 Jun 2020 02:46:58 +0100 Subject: [PATCH] add bit more TODO --- src/soc/fu/trap/main_stage.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index d9b0040a..a9f91954 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -124,7 +124,7 @@ class TrapMainStage(PipeModBase): with m.Case(InternalOp.OP_MTMSR): # TODO: some of the bits need zeroing? """ - if e_in.insn(16) = '1' then + if e_in.insn(16) = '1' then <-- this is X-form field "L". -- just update EE and RI ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE); ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI); @@ -140,7 +140,8 @@ class TrapMainStage(PipeModBase): ctrl_tmp.msr(MSR_DR) <= '1'; """ # TODO translate this: - # if e_in.insn(16) = '1' then + # L = self.fields.FormXL.L[0:-1] + # if e_in.insn(16) = '1' then <-- this is X-form field "L". # -- just update EE and RI # ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE); # ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI); -- 2.30.2