From 7a9031c48ed91de674f4ad1507b1148153930d0d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:22:53 -0700 Subject: [PATCH] Add CHANGELOG entry --- CHANGELOG | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index ca42df71e..92456df99 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "opt_share" pass, run as part of "opt -full" - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping - Removed "ice40_unlut" + - Added "xilinx_srl" for Xilinx shift register extraction + - Removed "shregmap -tech xilinx" Yosys 0.8 .. Yosys 0.8-dev -------------------------- -- 2.30.2