From 7a9d1be97d100c265530270810071e2e9e676b3e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Dec 2019 17:44:59 -0800
Subject: [PATCH] Add memory rules for RAM16X1D, RAM32M, RAM64M

---
 techlibs/xilinx/lutrams.txt   |  64 +++++++++++++++++++++
 techlibs/xilinx/lutrams_map.v | 104 ++++++++++++++++++++++++++++++++++
 2 files changed, 168 insertions(+)

diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt
index 2613c206c..3e260b0d7 100644
--- a/techlibs/xilinx/lutrams.txt
+++ b/techlibs/xilinx/lutrams.txt
@@ -1,4 +1,17 @@
 
+bram $__XILINX_RAM16X1D
+  init 1
+  abits 4
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
 bram $__XILINX_RAM32X1D
   init 1
   abits 5
@@ -38,6 +51,41 @@ bram $__XILINX_RAM128X1D
   clkpol 0 2
 endbram
 
+
+bram $__XILINX_RAM32M
+  init 1
+  abits 5
+  dbits 2
+  groups 2
+  ports  3 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+bram $__XILINX_RAM64M
+  init 1
+  abits 6
+  dbits 1
+  groups 2
+  ports  3 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+
+match $__XILINX_RAM16X1D
+  min bits 2
+  min wports 1
+  make_outreg
+  or_next_if_better
+endmatch
+
 match $__XILINX_RAM32X1D
   min bits 3
   min wports 1
@@ -56,5 +104,21 @@ match $__XILINX_RAM128X1D
   min bits 9
   min wports 1
   make_outreg
+  or_next_if_better
+endmatch
+
+
+match $__XILINX_RAM32M
+  min bits 5
+  min rports 3
+  min wports 1
+  make_outreg
+  or_next_if_better
 endmatch
 
+match $__XILINX_RAM64M
+  min bits 5
+  min rports 3
+  min wports 1
+  make_outreg
+endmatch
diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v
index 77041ca86..985e53ff4 100644
--- a/techlibs/xilinx/lutrams_map.v
+++ b/techlibs/xilinx/lutrams_map.v
@@ -1,4 +1,36 @@
 
+module \$__XILINX_RAM16X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [15:0] INIT = 16'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [3:0] A1ADDR;
+	output A1DATA;
+
+	input [3:0] B1ADDR;
+	input B1DATA;
+	input B1EN;
+
+	RAM16X1D #(
+		.INIT(INIT),
+		.IS_WCLK_INVERTED(!CLKPOL2)
+	) _TECHMAP_REPLACE_ (
+		.DPRA0(A1ADDR[0]),
+		.DPRA1(A1ADDR[1]),
+		.DPRA2(A1ADDR[2]),
+		.DPRA3(A1ADDR[3]),
+		.DPO(A1DATA),
+
+		.A0(B1ADDR[0]),
+		.A1(B1ADDR[1]),
+		.A2(B1ADDR[2]),
+		.A3(B1ADDR[3]),
+		.D(B1DATA),
+		.WCLK(CLK1),
+		.WE(B1EN)
+	);
+endmodule
+
 module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	parameter [31:0] INIT = 32'bx;
 	parameter CLKPOL2 = 1;
@@ -95,3 +127,75 @@ module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	);
 endmodule
 
+
+module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
+	parameter [31:0] INIT = 32'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [4:0] A1ADDR, A2ADDR, A3ADDR;
+	output [1:0] A1DATA, A2DATA, A3DATA;
+
+	input [4:0] B1ADDR;
+	input [1:0] B1DATA;
+	input B1EN;
+
+	RAM32M #(
+		.INIT_A(INIT),
+		.INIT_B(INIT),
+		.INIT_C(INIT),
+		.INIT_D(INIT),
+		.IS_WCLK_INVERTED(!CLKPOL2)
+	) _TECHMAP_REPLACE_ (
+		.ADDRA(A1ADDR),
+		.ADDRB(A2ADDR),
+		.ADDRC(A3ADDR),
+        .DOA(A1DATA),
+        .DOB(A2DATA),
+        .DOC(A3DATA),
+
+		.ADDRD(B1ADDR),
+		.DIA(B1DATA),
+		.DIB(B1DATA),
+		.DIC(B1DATA),
+		.DID(B1DATA),
+		.WCLK(CLK1),
+		.WE(B1EN)
+	);
+endmodule
+
+module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0] INIT = 32'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [5:0] A1ADDR, A2ADDR, A3ADDR;
+	output A1DATA, A2DATA, A3DATA;
+
+	input [5:0] B1ADDR;
+	input B1DATA;
+	input B1EN;
+
+	RAM64M #(
+		.INIT_A(INIT),
+		.INIT_B(INIT),
+		.INIT_C(INIT),
+		.INIT_D(INIT),
+		.IS_WCLK_INVERTED(!CLKPOL2)
+	) _TECHMAP_REPLACE_ (
+		.ADDRA(A1ADDR),
+		.ADDRB(A2ADDR),
+		.ADDRC(A3ADDR),
+        .DOA(A1DATA),
+        .DOB(A2DATA),
+        .DOC(A3DATA),
+
+		.ADDRD(B1ADDR),
+		.DIA(B1DATA),
+		.DIB(B1DATA),
+		.DIC(B1DATA),
+		.DID(B1DATA),
+		.WCLK(CLK1),
+		.WE(B1EN)
+	);
+endmodule
-- 
2.30.2