From 7aaa89ebb04208a2eaf6ef55cc34d1bbb7be0c4e Mon Sep 17 00:00:00 2001 From: Nicholas Calderwood Date: Sat, 14 Oct 2023 15:31:06 +0100 Subject: [PATCH] add english to lhzupx instruction --- openpower/isa/pifixedload.mdwn | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn index f67107fe..ab2477bc 100644 --- a/openpower/isa/pifixedload.mdwn +++ b/openpower/isa/pifixedload.mdwn @@ -98,6 +98,16 @@ Pseudo-code: RT <- ([0] * (XLEN-16)) || MEM(EA, 2) RA <- (RA) + (RB) +Description: + + Let the effective address (EA) be register RA. + The halfword in storage addressed by EA is loaded into + RT[48:63]. RT[0:47] are set to 0. + + The sum (RA) + (RB) is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered: None -- 2.30.2