From 7aac6c6e5801ee0c8f2410d09646a2b32d56edc0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 9 May 2022 00:11:51 +0100
Subject: [PATCH]

---
 openpower/sv/SimpleV_rationale.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index c61a03905..eb59d1ecd 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -928,7 +928,8 @@ a RADIX MMU and associated TLB-aware minimal L1 Cache, in order
 to support OpenCAPI properly? The answer is very likely to be yes.
 The saving grace here is that with
 the expectation of running only hot-loops with ZOLC-driven
-binaries, the size of L1 Cache needed would be miniscule compared
+binaries, the size of each PE's
+L1 Cache needed would be miniscule compared
 to the average high-end CPU.
 
 **Roadmap summary of Advanced SVP64**
-- 
2.30.2