From 7ad1028f8bbe875cc70ad350f9cf5aa5a6bb6323 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 20 Jun 2014 17:10:09 +0200 Subject: [PATCH] mibuild: use SimpleCRG instead of CRG_SE, remove period parameter for CRG_DS, clean up platforms --- examples/cordic/cordic_impl.py | 5 +++-- mibuild/altera_quartus.py | 6 ------ mibuild/platforms/de0nano.py | 5 +++-- mibuild/platforms/kc705.py | 10 ++++++++-- mibuild/platforms/lx9_microboard.py | 4 ++-- mibuild/platforms/m1.py | 4 ++-- mibuild/platforms/mixxeo.py | 4 ++-- mibuild/platforms/ml605.py | 8 +++++++- mibuild/platforms/papilio_pro.py | 4 ++-- mibuild/platforms/rhino.py | 8 +++++++- mibuild/platforms/zedboard.py | 4 ++-- mibuild/platforms/ztex_115d.py | 4 ++-- mibuild/xilinx_common.py | 9 +-------- mibuild/xilinx_ise.py | 5 +---- mibuild/xilinx_vivado.py | 7 ++----- 15 files changed, 44 insertions(+), 43 deletions(-) diff --git a/examples/cordic/cordic_impl.py b/examples/cordic/cordic_impl.py index 9cc79194..d4c2e066 100644 --- a/examples/cordic/cordic_impl.py +++ b/examples/cordic/cordic_impl.py @@ -5,7 +5,8 @@ from migen.fhdl.std import * from migen.genlib.cordic import Cordic from mibuild.tools import mkdir_noerror from mibuild.generic_platform import * -from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE +from mibuild.crg import SimpleCRG +from mibuild.xilinx_ise import XilinxISEPlatform class CordicImpl(Module): def __init__(self, name, **kwargs): @@ -38,7 +39,7 @@ class Platform(XilinxISEPlatform): ] def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io, - lambda p: CRG_SE(p, "clk", "rst", 10.)) + lambda p: SimpleCRG(p, "clk", "rst")) if __name__ == "__main__": default = dict(width=16, guard=0, eval_mode="pipelined", diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 24d0e8c2..2a5e7a8d 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -5,14 +5,8 @@ import os, subprocess from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild import tools -class CRG_SE(SimpleCRG): - def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): - SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - platform.add_period_constraint(platform, self.cd_sys.clk, period) - def _format_constraint(c): if isinstance(c, Pins): return "set_location_assignment PIN_" + c.identifiers[0] diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index b0906528..0fd93726 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -2,7 +2,8 @@ # License: BSD from mibuild.generic_platform import * -from mibuild.altera_quartus import AlteraQuartusPlatform, CRG_SE +from mibuild.crg import SimpleCRG +from mibuild.altera_quartus import AlteraQuartusPlatform _io = [ ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), @@ -92,7 +93,7 @@ _io = [ class Platform(AlteraQuartusPlatform): def __init__(self): AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io, - lambda p: CRG_SE(p, "clk50", None)) + lambda p: SimpleCRG(p, "clk50", None)) def do_finalize(self, fragment): try: diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 680de17b..fe6f91f1 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -1,5 +1,6 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_SE, CRG_DS +from mibuild.crg import SimpleCRG +from mibuild.xilinx_common import CRG_DS from mibuild.xilinx_ise import XilinxISEPlatform from mibuild.xilinx_vivado import XilinxVivadoPlatform @@ -90,7 +91,12 @@ def Platform(*args, toolchain="ise", **kwargs): raise ValueError class RealPlatform(xilinx_platform): - def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset", 6.4)): + def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")): xilinx_platform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory) + def do_finalize(self, fragment): + try: + self.add_period_constraint(self.lookup_request("clk156").p, 6.4) + except ConstraintError: + pass return RealPlatform(*args, **kwargs) diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index 660256cd..e259e4eb 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -1,5 +1,5 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_SE +from mibuild.crg import SimpleCRG from mibuild.xilinx_ise import XilinxISEPlatform _io = [ @@ -109,7 +109,7 @@ promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit """ def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io, - lambda p: CRG_SE(p, "clk_y3", "user_btn")) + lambda p: SimpleCRG(p, "clk_y3", "user_btn")) self.add_platform_command(""" CONFIG VCCAUX = "3.3"; """) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index 4d112d5b..fa4e4bee 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -1,5 +1,5 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_SE +from mibuild.crg import SimpleCRG from mibuild.xilinx_ise import XilinxISEPlatform _io = [ @@ -120,7 +120,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, - lambda p: CRG_SE(p, "clk50", None)) + lambda p: SimpleCRG(p, "clk50", None)) def do_finalize(self, fragment): try: diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index 298474a5..01f898d2 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -1,5 +1,5 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_SE +from mibuild.crg import SimpleCRG from mibuild.xilinx_ise import XilinxISEPlatform _io = [ @@ -156,7 +156,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, - lambda p: CRG_SE(p, "clk50", None)) + lambda p: SimpleCRG(p, "clk50", None)) self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") def do_finalize(self, fragment): diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py index 6b649baf..ab263909 100644 --- a/mibuild/platforms/ml605.py +++ b/mibuild/platforms/ml605.py @@ -54,4 +54,10 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io, - lambda p: CRG_DS(p, "clk200", "user_btn", 5.0)) + lambda p: CRG_DS(p, "clk200", "user_btn")) + + def do_finalize(self, fragment): + try: + self.add_period_constraint(self.lookup_request("clk200").p, 5) + except ConstraintError: + pass diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index 3e21f586..957d7cfe 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -1,5 +1,5 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_SE +from mibuild.crg import SimpleCRG from mibuild.xilinx_ise import XilinxISEPlatform _io = [ @@ -51,7 +51,7 @@ _connectors = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io, - lambda p: CRG_SE(p, "clk32", None), _connectors) + lambda p: SimpleCRG(p, "clk32", None), _connectors) def do_finalize(self, fragment): try: diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index 5af6ea3f..e0d05051 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -136,4 +136,10 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io, - lambda p: CRG_DS(p, "clk100", "gpio", 10.0)) + lambda p: CRG_DS(p, "clk100", "gpio")) + + def do_finalize(self, fragment): + try: + self.add_period_constraint(self.lookup_request("clk100").p, 10) + except ConstraintError: + pass diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py index eb89066e..33c9fc16 100644 --- a/mibuild/platforms/zedboard.py +++ b/mibuild/platforms/zedboard.py @@ -1,5 +1,5 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_SE +from mibuild.crg import SimpleCRG from mibuild.xilinx_ise import XilinxISEPlatform # Bank 34 and 35 voltage depend on J18 jumper setting @@ -140,7 +140,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io, - lambda p: CRG_SE(p, "clk100", None)) + lambda p: SimpleCRG(p, "clk100", None)) def do_finalize(self, fragment): try: diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py index 27de9362..ece202f6 100644 --- a/mibuild/platforms/ztex_115d.py +++ b/mibuild/platforms/ztex_115d.py @@ -1,5 +1,5 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_SE +from mibuild.crg import SimpleCRG from mibuild.xilinx_ise import XilinxISEPlatform _io = [ @@ -84,7 +84,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io, - lambda p: CRG_SE(p, "clk_if", "rst")) + lambda p: SimpleCRG(p, "clk_if", "rst")) self.add_platform_command(""" CONFIG VCCAUX = "2.5"; """) diff --git a/mibuild/xilinx_common.py b/mibuild/xilinx_common.py index aaec951f..b9452b72 100644 --- a/mibuild/xilinx_common.py +++ b/mibuild/xilinx_common.py @@ -1,17 +1,10 @@ from migen.fhdl.std import * -from mibuild.crg import SimpleCRG - -class CRG_SE(SimpleCRG): - def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): - SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - platform.add_period_constraint(platform, self._clk, period) class CRG_DS(Module): - def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): + def __init__(self, platform, clk_name, rst_name, rst_invert=False): reset_less = rst_name is None self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less) self._clk = platform.request(clk_name) - platform.add_period_constraint(platform, self._clk.p, period) self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p), Instance.Input("IB", self._clk.n), diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 5733a877..56bd414a 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -9,8 +9,6 @@ from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * from mibuild import tools -from mibuild.xilinx_common import CRG_SE, CRG_DS - def _format_constraint(c): if isinstance(c, Pins): return "LOC=" + c.identifiers[0] @@ -221,6 +219,5 @@ class XilinxISEPlatform(GenericPlatform): os.chdir("..") def add_period_constraint(self, clk, period): - if period is not None: - self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}"; + self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}"; TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk) diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py index 40c0a27d..e7421741 100644 --- a/mibuild/xilinx_vivado.py +++ b/mibuild/xilinx_vivado.py @@ -9,8 +9,6 @@ from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * from mibuild import tools -from mibuild.xilinx_common import CRG_SE, CRG_DS - def _format_constraint(c): if isinstance(c, Pins): return "set_property LOC " + c.identifiers[0] @@ -101,6 +99,5 @@ class XilinxVivadoPlatform(GenericPlatform): os.chdir("..") def add_period_constraint(self, clk, period): - if period is not None: - self.add_platform_command("""create_clock -name {clk} -period """ +\ - str(period) + """ [get_ports {clk}]""", clk=clk) + self.add_platform_command("""create_clock -name {clk} -period """ +\ + str(period) + """ [get_ports {clk}]""", clk=clk) -- 2.30.2