From 7ada0159fda8e470b40570089634b95f2d973600 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 19 May 2013 20:53:37 +0200 Subject: [PATCH] bus/csr/SRAM: support init --- migen/bus/csr.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/migen/bus/csr.py b/migen/bus/csr.py index 3062117d..1c3c3bd4 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -55,11 +55,11 @@ def _compute_page_bits(nwords): return 0 class SRAM(Module): - def __init__(self, mem_or_size, address, read_only=None, bus=None): + def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None): if isinstance(mem_or_size, Memory): mem = mem_or_size else: - mem = Memory(data_width, mem_or_size//(data_width//8)) + mem = Memory(data_width, mem_or_size//(data_width//8), init=init) if mem.width > data_width: csrw_per_memw = (mem.width + data_width - 1)//data_width word_bits = bits_for(csrw_per_memw-1) -- 2.30.2