From 7afa3d61d90eb43cc438573ad56278fe5173866c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 2 Jul 2015 09:32:33 +0200
Subject: [PATCH] mibuild/xilinx: Xilinx's FPGAs do not necessary share the
 same primitives: add xilinx_s7_special_overrides and specific
 XilinxDDROutputS7 implementation

Fix DDROutput implementation on spartan6 (tested with LiteETH's GMII phy)
---
 mibuild/xilinx/common.py   | 39 +++++++++++++++++++++++++++++---------
 mibuild/xilinx/platform.py |  2 ++
 2 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/mibuild/xilinx/common.py b/mibuild/xilinx/common.py
index 207711ef..ba125659 100644
--- a/mibuild/xilinx/common.py
+++ b/mibuild/xilinx/common.py
@@ -103,6 +103,31 @@ class XilinxDifferentialOutput:
 
 
 class XilinxDDROutputImpl(Module):
+    def __init__(self, i1, i2, o, clk):
+        self.specials += Instance("ODDR2",
+                p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
+                i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0,
+                i_D0=i1, i_D1=i2, o_Q=o,
+        )
+
+
+class XilinxDDROutput:
+    @staticmethod
+    def lower(dr):
+        return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
+
+
+xilinx_special_overrides = {
+    NoRetiming:             XilinxNoRetiming,
+    MultiReg:               XilinxMultiReg,
+    AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
+    DifferentialInput:      XilinxDifferentialInput,
+    DifferentialOutput:     XilinxDifferentialOutput,
+    DDROutput:              XilinxDDROutput
+}
+
+
+class XilinxDDROutputImplS7(Module):
     def __init__(self, i1, i2, o, clk):
         self.specials += Instance("ODDR",
                 p_DDR_CLK_EDGE="SAME_EDGE",
@@ -111,16 +136,12 @@ class XilinxDDROutputImpl(Module):
         )
 
 
-class XilinxDDROutput:
+class XilinxDDROutputS7:
     @staticmethod
     def lower(dr):
-        return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
+        return XilinxDDROutputImplS7(dr.i1, dr.i2, dr.o, dr.clk)
 
-xilinx_special_overrides = {
-    NoRetiming:                    XilinxNoRetiming,
-    MultiReg:                    XilinxMultiReg,
-    AsyncResetSynchronizer:        XilinxAsyncResetSynchronizer,
-    DifferentialInput:            XilinxDifferentialInput,
-    DifferentialOutput:            XilinxDifferentialOutput,
-    DDROutput:                    XilinxDDROutput
+
+xilinx_s7_special_overrides = {
+    DDROutput:              XilinxDDROutputS7
 }
diff --git a/mibuild/xilinx/platform.py b/mibuild/xilinx/platform.py
index cf202b17..201ad53a 100644
--- a/mibuild/xilinx/platform.py
+++ b/mibuild/xilinx/platform.py
@@ -16,6 +16,8 @@ class XilinxPlatform(GenericPlatform):
 
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         so = dict(common.xilinx_special_overrides)
+        if self.device[:3] == "xc7":
+            so.update(dict(common.xilinx_s7_special_overrides))
         so.update(special_overrides)
         return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
 
-- 
2.30.2