From 7afafa698ca76fa35bb78c7ef7809c81d7a26ad2 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 11 Jun 2022 11:13:40 +0100 Subject: [PATCH] --- openpower/sv/mv.swizzle.mdwn | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn index b02bfb777..a265a2a29 100644 --- a/openpower/sv/mv.swizzle.mdwn +++ b/openpower/sv/mv.swizzle.mdwn @@ -6,19 +6,14 @@ Links * -TODO: evaluate whether this will fit with [[mv.vec]] - the encoding embeds predication into the swizzle as well as constants 1/1.0 and 0/0.0 # Format -| 0.5 |6.10|11.15|16.20|21.....25|26.....30|31| name | -|-----|----|-----|-----|---------|---------|--|--------------| -| 19 | RT | RA | | XO[0:4] | XO[5:9] |Rc| XL-Form | -| 19 | RT | RA |imm | imm | 01 M im |0 | mv.vec.swiz | -| 19 | RT | RA |imm | imm | 01 M im |1 | fmv.vec.swiz | -| 19 | RT | RA |imm | imm | 11 0 im |0 | mv.swiz | -| 19 | RT | RA |imm | imm | 11 0 im |1 | fmv.swiz | +| 0.5 |6.10|11.15|16.27|28.31| name | +|-----|----|-----|-----|-----|--------------| +|PO | RT | RA |imm | 0011| mv.swiz | +|PO | RT | RA |imm | 1011| fmv.swiz | this gives a 12 bit immediate across bits 16 to 25 and 29-30. @@ -27,7 +22,7 @@ this gives a 12 bit immediate across bits 16 to 25 and 29-30. * 3 bits Z * 3 bits W -except that the options are: +the options are: * 0b000 to indicate "skip". this is equivalent to predicate masking * 0b001 is not needed (reserved) @@ -40,5 +35,3 @@ Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 c Note that 7 options are needed (not 6) because the 7th option allows predicate masking to be encoded within the swizzle immediate. For example this allows "W..Y" to be specified, "copy W to position X, and Y to position W, leave the other two positions Y and Z unaltered" - -Mode M is described in [[mv.vec]] and allows for merge and split of vectors. -- 2.30.2