From 7b25312da3de910628f855ff92a0ede642d8d9b5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Jun 2020 20:30:18 +0100 Subject: [PATCH] add pi.busy_o connection, increase to 64 bit --- src/soc/experiment/pi2ls.py | 6 ++++-- src/soc/experiment/test/test_pi2ls.py | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index f2c485c9..11cd1ab5 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -31,8 +31,9 @@ from nmigen import Elaboratable, Module, Signal class Pi2LSUI(Elaboratable): - def __init__(self, name, pi=None, lsui=None, regwid=64, addrwid=48): - self.addrbits = 4 + def __init__(self, name, pi=None, lsui=None, + regwid=64, mask_wid=8, addrwid=48): + self.addrbits = mask_wid if pi is None: pi = PortInterface(name="%s_pi", regwid=regwid, addrwid=addrwid) self.pi = pi @@ -52,6 +53,7 @@ class Pi2LSUI(Elaboratable): m.d.comb += lsui.x_ld_i.eq(pi.is_ld_i) m.d.comb += lsui.x_st_i.eq(pi.is_st_i) + m.d.comb += pi.busy_o.eq(lsui.x_busy_o) with m.If(pi.addr.ok): # expand the LSBs of address plus LD/ST len into 16-bit mask diff --git a/src/soc/experiment/test/test_pi2ls.py b/src/soc/experiment/test/test_pi2ls.py index 674d417c..705d691c 100644 --- a/src/soc/experiment/test/test_pi2ls.py +++ b/src/soc/experiment/test/test_pi2ls.py @@ -124,10 +124,11 @@ class TestPIMem(unittest.TestCase): def test_pi2ls(self): m = Module() - regwid = 32 - addrwid = 32 + regwid = 64 + addrwid = 48 m.submodules.dut = dut = Pi2LSUI("mem", regwid=regwid, addrwid=addrwid) m.submodules.lsmem = lsmem = TestMemLoadStoreUnit(addr_wid=addrwid, + mask_wid=8, data_wid=regwid) # Connect inputs -- 2.30.2