From 7b26332e21d47a840a6eb1fa4316209e0bed3470 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 8 May 2022 16:49:26 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index a70389608..9cc70584e 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -89,7 +89,8 @@ it. ARM's SVE/SVE2 is critically flawed (lacking the Cray `setvl` instruction that makes a truly ubiquitous Vector ISA) in ways that will become apparent over time as adoption increases. In the meantime programmers are, in direct violation of ARM's advice on how to use SVE2, -trying desperately to use it as if it was Packed SIMD NEON. The advice +trying desperately to understand it by applying their experience +of Packed SIMD NEON. The advice from ARM not to create SVE2 assembler that is hardcoded to fixed widths is being disregarded, in favour of writing *multiple identical implementations* of a function, each with a different hardware width, and compelling -- 2.30.2