From 7b2a0f880b5964d120d06d1661ee2701333d0e1e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 15 Jun 2020 22:21:50 -0400 Subject: [PATCH] radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state The si_shader pointer is already there, so use it and remove the array of BOs. Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_cp_dma.c | 3 +-- src/gallium/drivers/radeonsi/si_pm4.c | 20 +++---------------- src/gallium/drivers/radeonsi/si_pm4.h | 9 --------- .../drivers/radeonsi/si_state_shaders.c | 8 -------- 4 files changed, 4 insertions(+), 36 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 710dd332816..56d240c0a20 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -409,8 +409,7 @@ void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf static void cik_prefetch_shader_async(struct si_context *sctx, struct si_pm4_state *state) { - struct pipe_resource *bo = &state->bo[0]->b.b; - assert(state->nbo == 1); + struct pipe_resource *bo = &state->shader->bo->b.b; cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0); } diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index a409b6efdd6..a5d93071ecc 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -83,22 +83,8 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) si_pm4_cmd_end(state, false); } -void si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage, - enum radeon_bo_priority priority) -{ - unsigned idx = state->nbo++; - assert(idx < SI_PM4_MAX_BO); - - si_resource_reference(&state->bo[idx], bo); - state->bo_usage[idx] = usage; - state->bo_priority[idx] = priority; -} - void si_pm4_clear_state(struct si_pm4_state *state) { - for (int i = 0; i < state->nbo; ++i) - si_resource_reference(&state->bo[i], NULL); - state->nbo = 0; state->ndw = 0; } @@ -119,9 +105,9 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state) { struct radeon_cmdbuf *cs = sctx->gfx_cs; - for (int i = 0; i < state->nbo; ++i) { - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->bo[i], state->bo_usage[i], - state->bo_priority[i]); + if (state->shader) { + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->shader->bo, + RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); } radeon_emit_array(cs, state->pm4, state->ndw); diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h index 34dc9be8472..37ade60b25a 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.h +++ b/src/gallium/drivers/radeonsi/si_pm4.h @@ -28,7 +28,6 @@ #include "radeon/radeon_winsys.h" #define SI_PM4_MAX_DW 176 -#define SI_PM4_MAX_BO 3 // forward defines struct si_context; @@ -50,12 +49,6 @@ struct si_pm4_state { unsigned ndw; uint32_t pm4[SI_PM4_MAX_DW]; - /* BO's referenced by this state */ - unsigned nbo; - struct si_resource *bo[SI_PM4_MAX_BO]; - enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO]; - enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO]; - /* For shader states only */ struct si_shader *shader; struct si_atom atom; @@ -66,8 +59,6 @@ void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw); void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate); void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val); -void si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage, - enum radeon_bo_priority priority); void si_pm4_clear_state(struct si_pm4_state *state); void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index cee13524edc..61af8ce2893 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -479,8 +479,6 @@ static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader) return; va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); - si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40)); @@ -503,7 +501,6 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) return; va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); if (sscreen->info.chip_class >= GFX9) { if (sscreen->info.chip_class >= GFX10) { @@ -589,7 +586,6 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) pm4->atom.emit = si_emit_shader_es; va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); if (shader->selector->type == PIPE_SHADER_VERTEX) { vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false); @@ -818,7 +814,6 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0); va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); if (sscreen->info.chip_class >= GFX9) { unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]; @@ -1088,7 +1083,6 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader } va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); if (es_type == PIPE_SHADER_VERTEX) { es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false); @@ -1388,7 +1382,6 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, } va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); if (gs) { vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */ @@ -1641,7 +1634,6 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask; va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40)); -- 2.30.2