From 7b39dffd2047652e2f8a6a32d34350859f0fc763 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Tue, 28 Jul 2020 17:47:49 +0200 Subject: [PATCH] Remove classes for read and write ports, add parameter check to gramNativePort --- gram/common.py | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/gram/common.py b/gram/common.py index fe31422..3da6c7d 100644 --- a/gram/common.py +++ b/gram/common.py @@ -181,6 +181,9 @@ class gramNativePort(Settings): def __init__(self, mode, address_width, data_width, clock_domain="sync", id=0): self.set_attributes(locals()) + if mode not in ["both", "read", "write"]: + raise ValueError("mode must be either both/read/write, not {!r}".format(mode)) + self.lock = Signal() self.cmd = stream.Endpoint(cmd_description(address_width)) @@ -204,16 +207,6 @@ class gramNativePort(Settings): return self.cmd.addr[:cba_shift] -class gramNativeWritePort(gramNativePort): - def __init__(self, *args, **kwargs): - gramNativePort.__init__(self, "write", *args, **kwargs) - - -class gramNativeReadPort(gramNativePort): - def __init__(self, *args, **kwargs): - gramNativePort.__init__(self, "read", *args, **kwargs) - - # Timing Controllers ------------------------------------------------------------------------------- class tXXDController(Elaboratable): -- 2.30.2