From 7b6d0bb4e1562e83cf2d2a450c741c48426e838c Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 17:11:58 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 5ee47abc2..04d4b4671 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -161,9 +161,10 @@ the other space totalling two 75% Majors. Note critically that: -* SVP64 may **not** hold any Scalar operations. There is no free available space. +*Unlike EXT001 SVP64's 24-bits may **not** hold also any Scalar operations. + There is no free available space: a 25th bit would be required. The entire 24-bits is **required** for the abstracted Hardware-Looping Concept - **even when these 24-bits are zero* + **even when these 24-bits are zero** * Any Scalar 64-bit instruction (regardless of how it is encoded) is unsafe to then Vectorise because this creates the situation of Prefixed-Prefixed, resulting in deep complexity in Hardware Decode at a critical juncture, as -- 2.30.2