From 7b805e81461e52467e48413f6d112cb703c41b2f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 28 Aug 2021 19:02:01 +0100 Subject: [PATCH] --- openpower/sv/av_opcodes.mdwn | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn index a51acdb5c..470bcf1f1 100644 --- a/openpower/sv/av_opcodes.mdwn +++ b/openpower/sv/av_opcodes.mdwn @@ -98,7 +98,19 @@ signed and unsigned, 8/16/32: these are all of the form: result = (src1 > src2) ? src1 : src2 # max result = (src1 < src2) ? src1 : src2 # min -*These do not exist in the scalar INTEGER ISA and would need to be added* +*These do not exist in the scalar INTEGER ISA and would need to be added*. +There are additionally no scalar FP min/max, either. These also +need to be added. + +Also it makes sense for both the integer and FP variants +to have Rc=1 modes, where those modes are based on the +respective cmp (or fsel / isel) behaviour. In other words, +the Rc=1 setting is based on the *comparison* of the +two inputs, rather than on which of the two results was +returned by the min/max opcode. + + result = (src1 > src2) ? src1 : src2 # max + CR0 = CR_computr(src2-src1) # not based on result ## vmerge operations -- 2.30.2