From 7b88980d06d2526123965b86257ea4eb4ef86915 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 15 Mar 2019 18:16:25 +0100 Subject: [PATCH] vexriscv: allow user to use an external variant --- litex/soc/cores/cpu/vexriscv/core.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 3700bf44..5a1afedc 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -18,6 +18,9 @@ class VexRiscv(Module, AutoCSR): variant = "std_debug" if variant == "debug" else variant variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug") assert variant in variants, "Unsupported variant %s" % variant + self.platform = platform + self.variant = variant + self.external_variant = None self.reset = Signal() self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() @@ -59,9 +62,6 @@ class VexRiscv(Module, AutoCSR): if "debug" in variant: self.add_debug() - # add verilog sources - self.add_sources(platform, variant) - def add_debug(self): debug_reset = Signal() @@ -162,5 +162,11 @@ class VexRiscv(Module, AutoCSR): vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog") platform.add_source(os.path.join(vdir, cpu_filename)) + def use_external_variant(self, variant_filename): + self.external_variant = True + self.platform.add_source(variant_filename) + def do_finalize(self): + if not self.external_variant: + self.add_sources(self.platform, self.variant) self.specials += Instance("VexRiscv", **self.cpu_params) -- 2.30.2