From 7b945b19ad7cebebbaaf4eec44a7a572233ab91b Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Fri, 13 Dec 2019 16:37:17 +0000 Subject: [PATCH] Sub-dword vector multiply for amdgcn 2019-12-13 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (mulv64si3): Rename to ... (mul3): ... this, and implement sub-dword patterns. (mulv64si3_dup): Rename to ... (mul3_dup): ... this, and implement sub-dword patterns. From-SVN: r279374 --- gcc/ChangeLog | 7 +++++++ gcc/config/gcn/gcn-valu.md | 22 +++++++++++----------- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c40d936e6cb..88482c6a682 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-12-13 Andrew Stubbs + + * config/gcn/gcn-valu.md (mulv64si3): Rename to ... + (mul3): ... this, and implement sub-dword patterns. + (mulv64si3_dup): Rename to ... + (mul3_dup): ... this, and implement sub-dword patterns. + 2019-12-13 Jan Hubicka * ipa-utils.c (ipa_merge_profiles): Improve dumping; merge common diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index e1b3c71971f..42604466161 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1740,22 +1740,22 @@ [(set_attr "type" "vop3a") (set_attr "length" "8")]) -(define_insn "mulv64si3" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (mult:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA") - (match_operand:V64SI 2 "gcn_alu_operand" " vSvA")))] +(define_insn "mul3" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (mult:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA") + (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" " vSvA")))] "" "v_mul_lo_u32\t%0, %1, %2" [(set_attr "type" "vop3a") (set_attr "length" "8")]) -(define_insn "mulv64si3_dup" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (mult:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA") - (vec_duplicate:V64SI - (match_operand:SI 2 "gcn_alu_operand" " SvA"))))] +(define_insn "mul3_dup" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (mult:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA") + (vec_duplicate:VEC_ALL1REG_INT_MODE + (match_operand: 2 "gcn_alu_operand" " SvA"))))] "" "v_mul_lo_u32\t%0, %1, %2" [(set_attr "type" "vop3a") -- 2.30.2