From 7b98bc18993ec23224086b74b8eb1a81e756cbd4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 30 May 2020 23:31:25 +0100 Subject: [PATCH] select CR0 write out only when RC=1 --- src/soc/decoder/power_decoder2.py | 4 +++- src/soc/fu/alu/test/test_pipe_caller.py | 17 ++++++++--------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 53bb2e0f..dffc9da7 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -327,6 +327,7 @@ class DecodeCROut(Elaboratable): def __init__(self, dec): self.dec = dec + self.rc_in = Signal(reset_less=True) self.sel_in = Signal(CROutSel, reset_less=True) self.insn_in = Signal(32, reset_less=True) self.cr_bitfield = Data(3, "cr_bitfield") @@ -343,7 +344,7 @@ class DecodeCROut(Elaboratable): pass # No bitfield activated with m.Case(CROutSel.CR0): comb += self.cr_bitfield.data.eq(0) - comb += self.cr_bitfield.ok.eq(1) + comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1 with m.Case(CROutSel.BF): comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1]) comb += self.cr_bitfield.ok.eq(1) @@ -455,6 +456,7 @@ class PowerDecode2(Elaboratable): comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel comb += dec_cr_in.sel_in.eq(self.dec.op.cr_in) comb += dec_cr_out.sel_in.eq(self.dec.op.cr_out) + comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data) # decode LD/ST length with m.Switch(self.dec.op.ldst_len): diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index be966d33..34ae0eae 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -237,18 +237,17 @@ class TestRunner(FHDLTestCase): def check_extra_alu_outputs(self, alu, dec2, sim, code): rc = yield dec2.e.rc.data + op = yield dec2.e.insn_type + cridx_ok = yield dec2.e.write_cr.ok + cridx = yield dec2.e.write_cr.data + if rc: - cr_expected = sim.crl[0].get_range().value - cr_actual = yield alu.n.data_o.cr0.data - self.assertEqual(cr_expected, cr_actual, code) + self.assertEqual(cridx, 0, code) - op = yield dec2.e.insn_type - if op == InternalOp.OP_CMP.value or \ - op == InternalOp.OP_CMPEQB.value: - bf = yield dec2.dec.BF + if cridx_ok: + cr_expected = sim.crl[cridx].get_range().value cr_actual = yield alu.n.data_o.cr0.data - cr_expected = sim.crl[bf].get_range().value - self.assertEqual(cr_expected, cr_actual, code) + self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code)) cry_out = yield dec2.e.output_carry if cry_out: -- 2.30.2