From 7ba7a1cb99030fcda571bc9e3ce562d91ef192ac Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 1 Dec 2020 15:26:15 +0000 Subject: [PATCH] update setvl(i) pseudocode and format --- openpower/sv/setvl.mdwn | 46 +++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index fbd75fcc9..98e5991b8 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -8,29 +8,42 @@ See links: # Format -| 0..5 |6....10|11....16|17...20|21.22|23.24|25.26|27...30|31| name | -|------|-------|--------|-------|-----|-----|--|--|-------|--|---------| -| 19 | RT | RA | | XO[0:4] XO[5:10] |/ | XL-Form | -| 19 | (RT|0)| (RA|0) |vlimmed |// |vs|ms| NNNNN |/ | setvl/i | +| 0..5 |6....10|11....15|16.20|21.22.23.24..25|26......30|31| name | +|------|-------|--------|-----|---------------|----------|--|---------| +| 19 | RT | RA | | XO[0:4] | XO[5:10] |Rc| XL-Form | +| 19 | (RT|0)| (RA|0) |imm | imm // vs ms | NNNNNN |Rc| setvl/i | # Pseudocode // instruction fields: - rd = get_rt_field(); - ra = get_ra_field(); - vlimmed = get_immed_field(); - + rd = get_rt_field(); // bits 6..10 + ra = get_ra_field(); // bits 11..15 + vlimmed = get_immed_field(); // bits 16..22 + vs = get_vs_field(); // bit 24 + ms = get_ms_field(); // bit 25 + Rc = get_Rc_field(); // bit 31 + + // set VL (or not). + // 3 options: from SPR, from immed, from ra if vs { - VL = vlimmed - } else { - VL = SPR[SV_VL] + if ra == 0 { + VL = SPR[SV_VL] + } else { + VL = vlimmed + } + } elif ra != 0 { + VL = GPR[ra] } + + // set MVL (or not). + // 2 options: from SPR, from immed if ms { MVL = vlimmed } else { MVL = SPR[SV_MVL] } - // calculate VL + + // calculate (limit) VL VL = min(VL, MVL) // store VL, MVL @@ -38,7 +51,10 @@ See links: SPR[SV_MVL] = MVL // write rd - if rd != 0 { - // rd is not x0 - regs[rd] = VL; + if rt != 0 { + // rt is not zero + regs[rt] = VL; + if Rc { + // update CR from VL + } } -- 2.30.2