From 7bc34a9bc75ce0b5d672323c7d05797592697274 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 29 Jan 2020 08:31:41 +0100 Subject: [PATCH] integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM). When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted. --- litex/soc/integration/soc_core.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 6f61a213..33240ff2 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -87,7 +87,7 @@ class SoCCore(Module): # ROM parameters integrated_rom_size=0, integrated_rom_init=[], # SRAM parameters - integrated_sram_size=0, integrated_sram_init=[], + integrated_sram_size=0x1000, integrated_sram_init=[], # MAIN_RAM parameters integrated_main_ram_size=0, integrated_main_ram_init=[], # CSR parameters @@ -139,10 +139,8 @@ class SoCCore(Module): self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] - if cpu_type is not None and integrated_sram_size == 0: - integrated_sram_size = 0x1000 - self.integrated_sram_size = integrated_sram_size - self.integrated_main_ram_size = integrated_main_ram_size + self.integrated_sram_size = integrated_sram_size + self.integrated_main_ram_size = integrated_main_ram_size assert csr_data_width in [8, 16, 32] self.csr_data_width = csr_data_width -- 2.30.2