From 7bcdb8c5bbf9d3bedb9095601e6111c9ec232b52 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 11 Jun 2022 11:45:51 +0100 Subject: [PATCH] --- openpower/sv/mv.swizzle.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn index a265a2a29..a491bccb1 100644 --- a/openpower/sv/mv.swizzle.mdwn +++ b/openpower/sv/mv.swizzle.mdwn @@ -35,3 +35,18 @@ Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 c Note that 7 options are needed (not 6) because the 7th option allows predicate masking to be encoded within the swizzle immediate. For example this allows "W..Y" to be specified, "copy W to position X, and Y to position W, leave the other two positions Y and Z unaltered" + +# RM Mode Concept: + +MVRM-2P-2S1D: + +| Field Name | Field bits | Description | +|------------|------------|----------------------------| +| Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) | +| Rsrc_EXTRA2 | `12:13` | extends Rsrc (R\*\_EXTRA2 Encoding) | +| src_SUBVL | `14:15` | SUBVL for Source | +| MASK_SRC | `16:18` | Execution Mask for Source | + +The inclusion of a separate src SUBVL would allow either +`sv.mv.swiz RT.vecN RA.vecN` to mean contiguous sequential copy +or it could mean zip/unzip (pack/unpack). -- 2.30.2