From 7bed9a37d28e663376021d161a9ae6417da8599e Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 7 Mar 2020 22:00:42 +0000
Subject: [PATCH]

---
 openpower.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/openpower.mdwn b/openpower.mdwn
index 45ba0db77..0f0ca59a9 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -44,6 +44,10 @@ Thus it is completely unnecessary to add any vector opcodes - at all -
 saving hugely on both hardware and compiler development time when
 the concept is dropped on top of a pre-existing ISA.
 
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
 # Integer Overflow / Saturate
 
 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
-- 
2.30.2