From 7bf3676845bb61373a7691edd60913cab9b1771a Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Mon, 8 Jul 2019 12:31:38 +0200 Subject: [PATCH] v3d: emit correct lowering for logic ops with integer render targets Reviewed-by: Eric Anholt --- src/broadcom/compiler/nir_to_vir.c | 7 ++- .../compiler/v3d_nir_lower_logic_ops.c | 49 ++++++++++++++++--- 2 files changed, 47 insertions(+), 9 deletions(-) diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index 4f12110ded1..de80ab3f9e8 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -1686,8 +1686,11 @@ vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr) if (swap_rb) num_components = MAX2(num_components, 3); - bool is_int_format = (c->fs_key->int_color_rb & (1 << rt)) || - (c->fs_key->uint_color_rb & (1 << rt)); + nir_variable *var = c->output_color_var[rt]; + enum glsl_base_type type = glsl_get_base_type(var->type); + + bool is_int_format = type == GLSL_TYPE_INT || + type == GLSL_TYPE_UINT; bool is_32b_tlb_format = is_int_format || (c->fs_key->f32_color_rb & (1 << rt)); diff --git a/src/broadcom/compiler/v3d_nir_lower_logic_ops.c b/src/broadcom/compiler/v3d_nir_lower_logic_ops.c index 849e554e8b7..6da23df9731 100644 --- a/src/broadcom/compiler/v3d_nir_lower_logic_ops.c +++ b/src/broadcom/compiler/v3d_nir_lower_logic_ops.c @@ -164,17 +164,32 @@ v3d_nir_get_tlb_color(nir_builder *b, int rt, int sample) } static nir_ssa_def * -v3d_nir_emit_logic_op(struct v3d_compile *c, nir_builder *b, - nir_ssa_def *src, int rt, int sample) +v3d_emit_logic_op_raw(struct v3d_compile *c, nir_builder *b, + nir_ssa_def **src_chans, nir_ssa_def **dst_chans, + int rt, int sample) { - nir_ssa_def *dst = v3d_nir_get_tlb_color(b, rt, sample); + const uint8_t *fmt_swz = v3d_get_format_swizzle_for_rt(c, rt); - nir_ssa_def *src_chans[4], *dst_chans[4]; - for (unsigned i = 0; i < 4; i++) { - src_chans[i] = nir_channel(b, src, i); - dst_chans[i] = nir_channel(b, dst, i); + nir_ssa_def *op_res[4]; + for (int i = 0; i < 4; i++) { + nir_ssa_def *src = src_chans[i]; + nir_ssa_def *dst = + v3d_nir_get_swizzled_channel(b, dst_chans, fmt_swz[i]); + op_res[i] = v3d_logicop(b, c->fs_key->logicop_func, src, dst); } + nir_ssa_def *r[4]; + for (int i = 0; i < 4; i++) + r[i] = v3d_nir_get_swizzled_channel(b, op_res, fmt_swz[i]); + + return nir_vec4(b, r[0], r[1], r[2], r[3]); +} + +static nir_ssa_def * +v3d_emit_logic_op_unorm(struct v3d_compile *c, nir_builder *b, + nir_ssa_def **src_chans, nir_ssa_def **dst_chans, + int rt, int sample) +{ const uint8_t src_swz[4] = { 0, 1, 2, 3 }; nir_ssa_def *packed_src = v3d_nir_swizzle_and_pack(b, src_chans, src_swz); @@ -189,6 +204,26 @@ v3d_nir_emit_logic_op(struct v3d_compile *c, nir_builder *b, return v3d_nir_unpack_and_swizzle(b, packed_result, fmt_swz); } +static nir_ssa_def * +v3d_nir_emit_logic_op(struct v3d_compile *c, nir_builder *b, + nir_ssa_def *src, int rt, int sample) +{ + nir_ssa_def *dst = v3d_nir_get_tlb_color(b, rt, sample); + + nir_ssa_def *src_chans[4], *dst_chans[4]; + for (unsigned i = 0; i < 4; i++) { + src_chans[i] = nir_channel(b, src, i); + dst_chans[i] = nir_channel(b, dst, i); + } + + if (util_format_is_unorm(c->fs_key->color_fmt[rt].format)) { + return v3d_emit_logic_op_unorm(c, b, src_chans, dst_chans, + rt, 0); + } else { + return v3d_emit_logic_op_raw(c, b, src_chans, dst_chans, rt, 0); + } +} + static void v3d_nir_lower_logic_op_instr(struct v3d_compile *c, nir_builder *b, -- 2.30.2